stm32f0/stm32f0x2/stk/
csr.rs

1///Register `CSR` reader
2pub type R = crate::R<CSRrs>;
3///Register `CSR` writer
4pub type W = crate::W<CSRrs>;
5///Field `ENABLE` reader - Counter enable
6pub type ENABLE_R = crate::BitReader;
7///Field `ENABLE` writer - Counter enable
8pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `TICKINT` reader - SysTick exception request enable
10pub type TICKINT_R = crate::BitReader;
11///Field `TICKINT` writer - SysTick exception request enable
12pub type TICKINT_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CLKSOURCE` reader - Clock source selection
14pub type CLKSOURCE_R = crate::BitReader;
15///Field `CLKSOURCE` writer - Clock source selection
16pub type CLKSOURCE_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `COUNTFLAG` reader - COUNTFLAG
18pub type COUNTFLAG_R = crate::BitReader;
19///Field `COUNTFLAG` writer - COUNTFLAG
20pub type COUNTFLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    ///Bit 0 - Counter enable
23    #[inline(always)]
24    pub fn enable(&self) -> ENABLE_R {
25        ENABLE_R::new((self.bits & 1) != 0)
26    }
27    ///Bit 1 - SysTick exception request enable
28    #[inline(always)]
29    pub fn tickint(&self) -> TICKINT_R {
30        TICKINT_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    ///Bit 2 - Clock source selection
33    #[inline(always)]
34    pub fn clksource(&self) -> CLKSOURCE_R {
35        CLKSOURCE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    ///Bit 16 - COUNTFLAG
38    #[inline(always)]
39    pub fn countflag(&self) -> COUNTFLAG_R {
40        COUNTFLAG_R::new(((self.bits >> 16) & 1) != 0)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("CSR")
46            .field("enable", &self.enable())
47            .field("tickint", &self.tickint())
48            .field("clksource", &self.clksource())
49            .field("countflag", &self.countflag())
50            .finish()
51    }
52}
53impl W {
54    ///Bit 0 - Counter enable
55    #[inline(always)]
56    pub fn enable(&mut self) -> ENABLE_W<CSRrs> {
57        ENABLE_W::new(self, 0)
58    }
59    ///Bit 1 - SysTick exception request enable
60    #[inline(always)]
61    pub fn tickint(&mut self) -> TICKINT_W<CSRrs> {
62        TICKINT_W::new(self, 1)
63    }
64    ///Bit 2 - Clock source selection
65    #[inline(always)]
66    pub fn clksource(&mut self) -> CLKSOURCE_W<CSRrs> {
67        CLKSOURCE_W::new(self, 2)
68    }
69    ///Bit 16 - COUNTFLAG
70    #[inline(always)]
71    pub fn countflag(&mut self) -> COUNTFLAG_W<CSRrs> {
72        COUNTFLAG_W::new(self, 16)
73    }
74}
75/**SysTick control and status register
76
77You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#STK:CSR)*/
80pub struct CSRrs;
81impl crate::RegisterSpec for CSRrs {
82    type Ux = u32;
83}
84///`read()` method returns [`csr::R`](R) reader structure
85impl crate::Readable for CSRrs {}
86///`write(|w| ..)` method takes [`csr::W`](W) writer structure
87impl crate::Writable for CSRrs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets CSR to value 0
91impl crate::Resettable for CSRrs {}
stm32f0/stm32f0x2/stk/csr.rs

stm32f0/stm32f0x2/stk/
csr.rs
