stm32f0/stm32f0x2/rcc/
apb1rstr.rs

1///Register `APB1RSTR` reader
2pub type R = crate::R<APB1RSTRrs>;
3///Register `APB1RSTR` writer
4pub type W = crate::W<APB1RSTRrs>;
5/**Timer 2 reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2RST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<TIM2RST> for bool {
15    #[inline(always)]
16    fn from(variant: TIM2RST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `TIM2RST` reader - Timer 2 reset
21pub type TIM2RST_R = crate::BitReader<TIM2RST>;
22impl TIM2RST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<TIM2RST> {
26        match self.bits {
27            true => Some(TIM2RST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == TIM2RST::Reset
35    }
36}
37///Field `TIM2RST` writer - Timer 2 reset
38pub type TIM2RST_W<'a, REG> = crate::BitWriter<'a, REG, TIM2RST>;
39impl<'a, REG> TIM2RST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(TIM2RST::Reset)
47    }
48}
49///Field `TIM3RST` reader - Timer 3 reset
50pub use TIM2RST_R as TIM3RST_R;
51///Field `TIM6RST` reader - Timer 6 reset
52pub use TIM2RST_R as TIM6RST_R;
53///Field `TIM7RST` reader - TIM7 timer reset
54pub use TIM2RST_R as TIM7RST_R;
55///Field `TIM14RST` reader - Timer 14 reset
56pub use TIM2RST_R as TIM14RST_R;
57///Field `WWDGRST` reader - Window watchdog reset
58pub use TIM2RST_R as WWDGRST_R;
59///Field `SPI2RST` reader - SPI2 reset
60pub use TIM2RST_R as SPI2RST_R;
61///Field `USART2RST` reader - USART 2 reset
62pub use TIM2RST_R as USART2RST_R;
63///Field `USART3RST` reader - USART3 reset
64pub use TIM2RST_R as USART3RST_R;
65///Field `USART4RST` reader - USART4 reset
66pub use TIM2RST_R as USART4RST_R;
67///Field `USART5RST` reader - USART5 reset
68pub use TIM2RST_R as USART5RST_R;
69///Field `I2C1RST` reader - I2C1 reset
70pub use TIM2RST_R as I2C1RST_R;
71///Field `I2C2RST` reader - I2C2 reset
72pub use TIM2RST_R as I2C2RST_R;
73///Field `USBRST` reader - USB interface reset
74pub use TIM2RST_R as USBRST_R;
75///Field `CANRST` reader - CAN interface reset
76pub use TIM2RST_R as CANRST_R;
77///Field `CRSRST` reader - Clock Recovery System interface reset
78pub use TIM2RST_R as CRSRST_R;
79///Field `PWRRST` reader - Power interface reset
80pub use TIM2RST_R as PWRRST_R;
81///Field `DACRST` reader - DAC interface reset
82pub use TIM2RST_R as DACRST_R;
83///Field `CECRST` reader - HDMI CEC reset
84pub use TIM2RST_R as CECRST_R;
85///Field `TIM3RST` writer - Timer 3 reset
86pub use TIM2RST_W as TIM3RST_W;
87///Field `TIM6RST` writer - Timer 6 reset
88pub use TIM2RST_W as TIM6RST_W;
89///Field `TIM7RST` writer - TIM7 timer reset
90pub use TIM2RST_W as TIM7RST_W;
91///Field `TIM14RST` writer - Timer 14 reset
92pub use TIM2RST_W as TIM14RST_W;
93///Field `WWDGRST` writer - Window watchdog reset
94pub use TIM2RST_W as WWDGRST_W;
95///Field `SPI2RST` writer - SPI2 reset
96pub use TIM2RST_W as SPI2RST_W;
97///Field `USART2RST` writer - USART 2 reset
98pub use TIM2RST_W as USART2RST_W;
99///Field `USART3RST` writer - USART3 reset
100pub use TIM2RST_W as USART3RST_W;
101///Field `USART4RST` writer - USART4 reset
102pub use TIM2RST_W as USART4RST_W;
103///Field `USART5RST` writer - USART5 reset
104pub use TIM2RST_W as USART5RST_W;
105///Field `I2C1RST` writer - I2C1 reset
106pub use TIM2RST_W as I2C1RST_W;
107///Field `I2C2RST` writer - I2C2 reset
108pub use TIM2RST_W as I2C2RST_W;
109///Field `USBRST` writer - USB interface reset
110pub use TIM2RST_W as USBRST_W;
111///Field `CANRST` writer - CAN interface reset
112pub use TIM2RST_W as CANRST_W;
113///Field `CRSRST` writer - Clock Recovery System interface reset
114pub use TIM2RST_W as CRSRST_W;
115///Field `PWRRST` writer - Power interface reset
116pub use TIM2RST_W as PWRRST_W;
117///Field `DACRST` writer - DAC interface reset
118pub use TIM2RST_W as DACRST_W;
119///Field `CECRST` writer - HDMI CEC reset
120pub use TIM2RST_W as CECRST_W;
121impl R {
122    ///Bit 0 - Timer 2 reset
123    #[inline(always)]
124    pub fn tim2rst(&self) -> TIM2RST_R {
125        TIM2RST_R::new((self.bits & 1) != 0)
126    }
127    ///Bit 1 - Timer 3 reset
128    #[inline(always)]
129    pub fn tim3rst(&self) -> TIM3RST_R {
130        TIM3RST_R::new(((self.bits >> 1) & 1) != 0)
131    }
132    ///Bit 4 - Timer 6 reset
133    #[inline(always)]
134    pub fn tim6rst(&self) -> TIM6RST_R {
135        TIM6RST_R::new(((self.bits >> 4) & 1) != 0)
136    }
137    ///Bit 5 - TIM7 timer reset
138    #[inline(always)]
139    pub fn tim7rst(&self) -> TIM7RST_R {
140        TIM7RST_R::new(((self.bits >> 5) & 1) != 0)
141    }
142    ///Bit 8 - Timer 14 reset
143    #[inline(always)]
144    pub fn tim14rst(&self) -> TIM14RST_R {
145        TIM14RST_R::new(((self.bits >> 8) & 1) != 0)
146    }
147    ///Bit 11 - Window watchdog reset
148    #[inline(always)]
149    pub fn wwdgrst(&self) -> WWDGRST_R {
150        WWDGRST_R::new(((self.bits >> 11) & 1) != 0)
151    }
152    ///Bit 14 - SPI2 reset
153    #[inline(always)]
154    pub fn spi2rst(&self) -> SPI2RST_R {
155        SPI2RST_R::new(((self.bits >> 14) & 1) != 0)
156    }
157    ///Bit 17 - USART 2 reset
158    #[inline(always)]
159    pub fn usart2rst(&self) -> USART2RST_R {
160        USART2RST_R::new(((self.bits >> 17) & 1) != 0)
161    }
162    ///Bit 18 - USART3 reset
163    #[inline(always)]
164    pub fn usart3rst(&self) -> USART3RST_R {
165        USART3RST_R::new(((self.bits >> 18) & 1) != 0)
166    }
167    ///Bit 19 - USART4 reset
168    #[inline(always)]
169    pub fn usart4rst(&self) -> USART4RST_R {
170        USART4RST_R::new(((self.bits >> 19) & 1) != 0)
171    }
172    ///Bit 20 - USART5 reset
173    #[inline(always)]
174    pub fn usart5rst(&self) -> USART5RST_R {
175        USART5RST_R::new(((self.bits >> 20) & 1) != 0)
176    }
177    ///Bit 21 - I2C1 reset
178    #[inline(always)]
179    pub fn i2c1rst(&self) -> I2C1RST_R {
180        I2C1RST_R::new(((self.bits >> 21) & 1) != 0)
181    }
182    ///Bit 22 - I2C2 reset
183    #[inline(always)]
184    pub fn i2c2rst(&self) -> I2C2RST_R {
185        I2C2RST_R::new(((self.bits >> 22) & 1) != 0)
186    }
187    ///Bit 23 - USB interface reset
188    #[inline(always)]
189    pub fn usbrst(&self) -> USBRST_R {
190        USBRST_R::new(((self.bits >> 23) & 1) != 0)
191    }
192    ///Bit 25 - CAN interface reset
193    #[inline(always)]
194    pub fn canrst(&self) -> CANRST_R {
195        CANRST_R::new(((self.bits >> 25) & 1) != 0)
196    }
197    ///Bit 27 - Clock Recovery System interface reset
198    #[inline(always)]
199    pub fn crsrst(&self) -> CRSRST_R {
200        CRSRST_R::new(((self.bits >> 27) & 1) != 0)
201    }
202    ///Bit 28 - Power interface reset
203    #[inline(always)]
204    pub fn pwrrst(&self) -> PWRRST_R {
205        PWRRST_R::new(((self.bits >> 28) & 1) != 0)
206    }
207    ///Bit 29 - DAC interface reset
208    #[inline(always)]
209    pub fn dacrst(&self) -> DACRST_R {
210        DACRST_R::new(((self.bits >> 29) & 1) != 0)
211    }
212    ///Bit 30 - HDMI CEC reset
213    #[inline(always)]
214    pub fn cecrst(&self) -> CECRST_R {
215        CECRST_R::new(((self.bits >> 30) & 1) != 0)
216    }
217}
218impl core::fmt::Debug for R {
219    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
220        f.debug_struct("APB1RSTR")
221            .field("tim2rst", &self.tim2rst())
222            .field("tim3rst", &self.tim3rst())
223            .field("tim6rst", &self.tim6rst())
224            .field("tim7rst", &self.tim7rst())
225            .field("tim14rst", &self.tim14rst())
226            .field("wwdgrst", &self.wwdgrst())
227            .field("spi2rst", &self.spi2rst())
228            .field("usart2rst", &self.usart2rst())
229            .field("usart3rst", &self.usart3rst())
230            .field("usart4rst", &self.usart4rst())
231            .field("i2c1rst", &self.i2c1rst())
232            .field("i2c2rst", &self.i2c2rst())
233            .field("usbrst", &self.usbrst())
234            .field("canrst", &self.canrst())
235            .field("crsrst", &self.crsrst())
236            .field("pwrrst", &self.pwrrst())
237            .field("dacrst", &self.dacrst())
238            .field("cecrst", &self.cecrst())
239            .field("usart5rst", &self.usart5rst())
240            .finish()
241    }
242}
243impl W {
244    ///Bit 0 - Timer 2 reset
245    #[inline(always)]
246    pub fn tim2rst(&mut self) -> TIM2RST_W<APB1RSTRrs> {
247        TIM2RST_W::new(self, 0)
248    }
249    ///Bit 1 - Timer 3 reset
250    #[inline(always)]
251    pub fn tim3rst(&mut self) -> TIM3RST_W<APB1RSTRrs> {
252        TIM3RST_W::new(self, 1)
253    }
254    ///Bit 4 - Timer 6 reset
255    #[inline(always)]
256    pub fn tim6rst(&mut self) -> TIM6RST_W<APB1RSTRrs> {
257        TIM6RST_W::new(self, 4)
258    }
259    ///Bit 5 - TIM7 timer reset
260    #[inline(always)]
261    pub fn tim7rst(&mut self) -> TIM7RST_W<APB1RSTRrs> {
262        TIM7RST_W::new(self, 5)
263    }
264    ///Bit 8 - Timer 14 reset
265    #[inline(always)]
266    pub fn tim14rst(&mut self) -> TIM14RST_W<APB1RSTRrs> {
267        TIM14RST_W::new(self, 8)
268    }
269    ///Bit 11 - Window watchdog reset
270    #[inline(always)]
271    pub fn wwdgrst(&mut self) -> WWDGRST_W<APB1RSTRrs> {
272        WWDGRST_W::new(self, 11)
273    }
274    ///Bit 14 - SPI2 reset
275    #[inline(always)]
276    pub fn spi2rst(&mut self) -> SPI2RST_W<APB1RSTRrs> {
277        SPI2RST_W::new(self, 14)
278    }
279    ///Bit 17 - USART 2 reset
280    #[inline(always)]
281    pub fn usart2rst(&mut self) -> USART2RST_W<APB1RSTRrs> {
282        USART2RST_W::new(self, 17)
283    }
284    ///Bit 18 - USART3 reset
285    #[inline(always)]
286    pub fn usart3rst(&mut self) -> USART3RST_W<APB1RSTRrs> {
287        USART3RST_W::new(self, 18)
288    }
289    ///Bit 19 - USART4 reset
290    #[inline(always)]
291    pub fn usart4rst(&mut self) -> USART4RST_W<APB1RSTRrs> {
292        USART4RST_W::new(self, 19)
293    }
294    ///Bit 20 - USART5 reset
295    #[inline(always)]
296    pub fn usart5rst(&mut self) -> USART5RST_W<APB1RSTRrs> {
297        USART5RST_W::new(self, 20)
298    }
299    ///Bit 21 - I2C1 reset
300    #[inline(always)]
301    pub fn i2c1rst(&mut self) -> I2C1RST_W<APB1RSTRrs> {
302        I2C1RST_W::new(self, 21)
303    }
304    ///Bit 22 - I2C2 reset
305    #[inline(always)]
306    pub fn i2c2rst(&mut self) -> I2C2RST_W<APB1RSTRrs> {
307        I2C2RST_W::new(self, 22)
308    }
309    ///Bit 23 - USB interface reset
310    #[inline(always)]
311    pub fn usbrst(&mut self) -> USBRST_W<APB1RSTRrs> {
312        USBRST_W::new(self, 23)
313    }
314    ///Bit 25 - CAN interface reset
315    #[inline(always)]
316    pub fn canrst(&mut self) -> CANRST_W<APB1RSTRrs> {
317        CANRST_W::new(self, 25)
318    }
319    ///Bit 27 - Clock Recovery System interface reset
320    #[inline(always)]
321    pub fn crsrst(&mut self) -> CRSRST_W<APB1RSTRrs> {
322        CRSRST_W::new(self, 27)
323    }
324    ///Bit 28 - Power interface reset
325    #[inline(always)]
326    pub fn pwrrst(&mut self) -> PWRRST_W<APB1RSTRrs> {
327        PWRRST_W::new(self, 28)
328    }
329    ///Bit 29 - DAC interface reset
330    #[inline(always)]
331    pub fn dacrst(&mut self) -> DACRST_W<APB1RSTRrs> {
332        DACRST_W::new(self, 29)
333    }
334    ///Bit 30 - HDMI CEC reset
335    #[inline(always)]
336    pub fn cecrst(&mut self) -> CECRST_W<APB1RSTRrs> {
337        CECRST_W::new(self, 30)
338    }
339}
340/**APB1 peripheral reset register (RCC_APB1RSTR)
341
342You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
343
344See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#RCC:APB1RSTR)*/
345pub struct APB1RSTRrs;
346impl crate::RegisterSpec for APB1RSTRrs {
347    type Ux = u32;
348}
349///`read()` method returns [`apb1rstr::R`](R) reader structure
350impl crate::Readable for APB1RSTRrs {}
351///`write(|w| ..)` method takes [`apb1rstr::W`](W) writer structure
352impl crate::Writable for APB1RSTRrs {
353    type Safety = crate::Unsafe;
354}
355///`reset()` method sets APB1RSTR to value 0
356impl crate::Resettable for APB1RSTRrs {}
stm32f0/stm32f0x2/rcc/apb1rstr.rs

stm32f0/stm32f0x2/rcc/
apb1rstr.rs
