stm32f0/stm32f0x2/comp/
csr.rs

1///Register `CSR` reader
2pub type R = crate::R<CSRrs>;
3///Register `CSR` writer
4pub type W = crate::W<CSRrs>;
5/**Comparator 1 enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum COMP1EN {
11    ///0: Comparator 1 disabled
12    Disabled = 0,
13    ///1: Comparator 1 enabled
14    Enabled = 1,
15}
16impl From<COMP1EN> for bool {
17    #[inline(always)]
18    fn from(variant: COMP1EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `COMP1EN` reader - Comparator 1 enable
23pub type COMP1EN_R = crate::BitReader<COMP1EN>;
24impl COMP1EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> COMP1EN {
28        match self.bits {
29            false => COMP1EN::Disabled,
30            true => COMP1EN::Enabled,
31        }
32    }
33    ///Comparator 1 disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == COMP1EN::Disabled
37    }
38    ///Comparator 1 enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == COMP1EN::Enabled
42    }
43}
44///Field `COMP1EN` writer - Comparator 1 enable
45pub type COMP1EN_W<'a, REG> = crate::BitWriter<'a, REG, COMP1EN>;
46impl<'a, REG> COMP1EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Comparator 1 disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(COMP1EN::Disabled)
54    }
55    ///Comparator 1 enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(COMP1EN::Enabled)
59    }
60}
61/**Comparator 1 non inverting input DAC switch
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum COMP1SW1 {
67    ///0: Switch open
68    Open = 0,
69    ///1: Switch closed
70    Closed = 1,
71}
72impl From<COMP1SW1> for bool {
73    #[inline(always)]
74    fn from(variant: COMP1SW1) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `COMP1SW1` reader - Comparator 1 non inverting input DAC switch
79pub type COMP1SW1_R = crate::BitReader<COMP1SW1>;
80impl COMP1SW1_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> COMP1SW1 {
84        match self.bits {
85            false => COMP1SW1::Open,
86            true => COMP1SW1::Closed,
87        }
88    }
89    ///Switch open
90    #[inline(always)]
91    pub fn is_open(&self) -> bool {
92        *self == COMP1SW1::Open
93    }
94    ///Switch closed
95    #[inline(always)]
96    pub fn is_closed(&self) -> bool {
97        *self == COMP1SW1::Closed
98    }
99}
100///Field `COMP1SW1` writer - Comparator 1 non inverting input DAC switch
101pub type COMP1SW1_W<'a, REG> = crate::BitWriter<'a, REG, COMP1SW1>;
102impl<'a, REG> COMP1SW1_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Switch open
107    #[inline(always)]
108    pub fn open(self) -> &'a mut crate::W<REG> {
109        self.variant(COMP1SW1::Open)
110    }
111    ///Switch closed
112    #[inline(always)]
113    pub fn closed(self) -> &'a mut crate::W<REG> {
114        self.variant(COMP1SW1::Closed)
115    }
116}
117/**Comparator 1 mode
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122#[repr(u8)]
123pub enum COMP1MODE {
124    ///0: High speed / full power
125    HighSpeed = 0,
126    ///1: Medium speed / medium power
127    MediumSpeed = 1,
128    ///2: Low speed / low power
129    LowSpeed = 2,
130    ///3: Very-low speed / ultra-low power
131    VeryLowSpeed = 3,
132}
133impl From<COMP1MODE> for u8 {
134    #[inline(always)]
135    fn from(variant: COMP1MODE) -> Self {
136        variant as _
137    }
138}
139impl crate::FieldSpec for COMP1MODE {
140    type Ux = u8;
141}
142impl crate::IsEnum for COMP1MODE {}
143///Field `COMP1MODE` reader - Comparator 1 mode
144pub type COMP1MODE_R = crate::FieldReader<COMP1MODE>;
145impl COMP1MODE_R {
146    ///Get enumerated values variant
147    #[inline(always)]
148    pub const fn variant(&self) -> COMP1MODE {
149        match self.bits {
150            0 => COMP1MODE::HighSpeed,
151            1 => COMP1MODE::MediumSpeed,
152            2 => COMP1MODE::LowSpeed,
153            3 => COMP1MODE::VeryLowSpeed,
154            _ => unreachable!(),
155        }
156    }
157    ///High speed / full power
158    #[inline(always)]
159    pub fn is_high_speed(&self) -> bool {
160        *self == COMP1MODE::HighSpeed
161    }
162    ///Medium speed / medium power
163    #[inline(always)]
164    pub fn is_medium_speed(&self) -> bool {
165        *self == COMP1MODE::MediumSpeed
166    }
167    ///Low speed / low power
168    #[inline(always)]
169    pub fn is_low_speed(&self) -> bool {
170        *self == COMP1MODE::LowSpeed
171    }
172    ///Very-low speed / ultra-low power
173    #[inline(always)]
174    pub fn is_very_low_speed(&self) -> bool {
175        *self == COMP1MODE::VeryLowSpeed
176    }
177}
178///Field `COMP1MODE` writer - Comparator 1 mode
179pub type COMP1MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COMP1MODE, crate::Safe>;
180impl<'a, REG> COMP1MODE_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183    REG::Ux: From<u8>,
184{
185    ///High speed / full power
186    #[inline(always)]
187    pub fn high_speed(self) -> &'a mut crate::W<REG> {
188        self.variant(COMP1MODE::HighSpeed)
189    }
190    ///Medium speed / medium power
191    #[inline(always)]
192    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
193        self.variant(COMP1MODE::MediumSpeed)
194    }
195    ///Low speed / low power
196    #[inline(always)]
197    pub fn low_speed(self) -> &'a mut crate::W<REG> {
198        self.variant(COMP1MODE::LowSpeed)
199    }
200    ///Very-low speed / ultra-low power
201    #[inline(always)]
202    pub fn very_low_speed(self) -> &'a mut crate::W<REG> {
203        self.variant(COMP1MODE::VeryLowSpeed)
204    }
205}
206/**Comparator 1 inverting input selection
207
208Value on reset: 0*/
209#[cfg_attr(feature = "defmt", derive(defmt::Format))]
210#[derive(Clone, Copy, Debug, PartialEq, Eq)]
211#[repr(u8)]
212pub enum COMP1INSEL {
213    ///0: 1/4 of VRefint
214    OneQuarterVref = 0,
215    ///1: 1/2 of VRefint
216    OneHalfVref = 1,
217    ///2: 3/4 of VRefint
218    ThreeQuarterVref = 2,
219    ///3: VRefint
220    Vref = 3,
221    ///4: COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
222    Comp1Inm4 = 4,
223    ///5: COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
224    Comp1Inm5 = 5,
225    ///6: COMP1_INM6 (PA0)
226    Comp1Inm6 = 6,
227}
228impl From<COMP1INSEL> for u8 {
229    #[inline(always)]
230    fn from(variant: COMP1INSEL) -> Self {
231        variant as _
232    }
233}
234impl crate::FieldSpec for COMP1INSEL {
235    type Ux = u8;
236}
237impl crate::IsEnum for COMP1INSEL {}
238///Field `COMP1INSEL` reader - Comparator 1 inverting input selection
239pub type COMP1INSEL_R = crate::FieldReader<COMP1INSEL>;
240impl COMP1INSEL_R {
241    ///Get enumerated values variant
242    #[inline(always)]
243    pub const fn variant(&self) -> Option<COMP1INSEL> {
244        match self.bits {
245            0 => Some(COMP1INSEL::OneQuarterVref),
246            1 => Some(COMP1INSEL::OneHalfVref),
247            2 => Some(COMP1INSEL::ThreeQuarterVref),
248            3 => Some(COMP1INSEL::Vref),
249            4 => Some(COMP1INSEL::Comp1Inm4),
250            5 => Some(COMP1INSEL::Comp1Inm5),
251            6 => Some(COMP1INSEL::Comp1Inm6),
252            _ => None,
253        }
254    }
255    ///1/4 of VRefint
256    #[inline(always)]
257    pub fn is_one_quarter_vref(&self) -> bool {
258        *self == COMP1INSEL::OneQuarterVref
259    }
260    ///1/2 of VRefint
261    #[inline(always)]
262    pub fn is_one_half_vref(&self) -> bool {
263        *self == COMP1INSEL::OneHalfVref
264    }
265    ///3/4 of VRefint
266    #[inline(always)]
267    pub fn is_three_quarter_vref(&self) -> bool {
268        *self == COMP1INSEL::ThreeQuarterVref
269    }
270    ///VRefint
271    #[inline(always)]
272    pub fn is_vref(&self) -> bool {
273        *self == COMP1INSEL::Vref
274    }
275    ///COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
276    #[inline(always)]
277    pub fn is_comp1_inm4(&self) -> bool {
278        *self == COMP1INSEL::Comp1Inm4
279    }
280    ///COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
281    #[inline(always)]
282    pub fn is_comp1_inm5(&self) -> bool {
283        *self == COMP1INSEL::Comp1Inm5
284    }
285    ///COMP1_INM6 (PA0)
286    #[inline(always)]
287    pub fn is_comp1_inm6(&self) -> bool {
288        *self == COMP1INSEL::Comp1Inm6
289    }
290}
291///Field `COMP1INSEL` writer - Comparator 1 inverting input selection
292pub type COMP1INSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, COMP1INSEL>;
293impl<'a, REG> COMP1INSEL_W<'a, REG>
294where
295    REG: crate::Writable + crate::RegisterSpec,
296    REG::Ux: From<u8>,
297{
298    ///1/4 of VRefint
299    #[inline(always)]
300    pub fn one_quarter_vref(self) -> &'a mut crate::W<REG> {
301        self.variant(COMP1INSEL::OneQuarterVref)
302    }
303    ///1/2 of VRefint
304    #[inline(always)]
305    pub fn one_half_vref(self) -> &'a mut crate::W<REG> {
306        self.variant(COMP1INSEL::OneHalfVref)
307    }
308    ///3/4 of VRefint
309    #[inline(always)]
310    pub fn three_quarter_vref(self) -> &'a mut crate::W<REG> {
311        self.variant(COMP1INSEL::ThreeQuarterVref)
312    }
313    ///VRefint
314    #[inline(always)]
315    pub fn vref(self) -> &'a mut crate::W<REG> {
316        self.variant(COMP1INSEL::Vref)
317    }
318    ///COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
319    #[inline(always)]
320    pub fn comp1_inm4(self) -> &'a mut crate::W<REG> {
321        self.variant(COMP1INSEL::Comp1Inm4)
322    }
323    ///COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
324    #[inline(always)]
325    pub fn comp1_inm5(self) -> &'a mut crate::W<REG> {
326        self.variant(COMP1INSEL::Comp1Inm5)
327    }
328    ///COMP1_INM6 (PA0)
329    #[inline(always)]
330    pub fn comp1_inm6(self) -> &'a mut crate::W<REG> {
331        self.variant(COMP1INSEL::Comp1Inm6)
332    }
333}
334/**Comparator 1 output selection
335
336Value on reset: 0*/
337#[cfg_attr(feature = "defmt", derive(defmt::Format))]
338#[derive(Clone, Copy, Debug, PartialEq, Eq)]
339#[repr(u8)]
340pub enum COMP1OUTSEL {
341    ///0: No selection
342    NoSelection = 0,
343    ///1: Timer 1 break input
344    Timer1breakInput = 1,
345    ///2: Timer 1 Input capture 1
346    Timer1inputCapture1 = 2,
347    ///3: Timer 1 OCrefclear input
348    Timer1ocrefClearInput = 3,
349    ///4: Timer 2 input capture 4
350    Timer2inputCapture4 = 4,
351    ///5: Timer 2 OCrefclear input
352    Timer2ocrefClearInput = 5,
353    ///6: Timer 3 input capture 1
354    Timer3inputCapture1 = 6,
355    ///7: Timer 3 OCrefclear input
356    Timer3ocrefClearInput = 7,
357}
358impl From<COMP1OUTSEL> for u8 {
359    #[inline(always)]
360    fn from(variant: COMP1OUTSEL) -> Self {
361        variant as _
362    }
363}
364impl crate::FieldSpec for COMP1OUTSEL {
365    type Ux = u8;
366}
367impl crate::IsEnum for COMP1OUTSEL {}
368///Field `COMP1OUTSEL` reader - Comparator 1 output selection
369pub type COMP1OUTSEL_R = crate::FieldReader<COMP1OUTSEL>;
370impl COMP1OUTSEL_R {
371    ///Get enumerated values variant
372    #[inline(always)]
373    pub const fn variant(&self) -> COMP1OUTSEL {
374        match self.bits {
375            0 => COMP1OUTSEL::NoSelection,
376            1 => COMP1OUTSEL::Timer1breakInput,
377            2 => COMP1OUTSEL::Timer1inputCapture1,
378            3 => COMP1OUTSEL::Timer1ocrefClearInput,
379            4 => COMP1OUTSEL::Timer2inputCapture4,
380            5 => COMP1OUTSEL::Timer2ocrefClearInput,
381            6 => COMP1OUTSEL::Timer3inputCapture1,
382            7 => COMP1OUTSEL::Timer3ocrefClearInput,
383            _ => unreachable!(),
384        }
385    }
386    ///No selection
387    #[inline(always)]
388    pub fn is_no_selection(&self) -> bool {
389        *self == COMP1OUTSEL::NoSelection
390    }
391    ///Timer 1 break input
392    #[inline(always)]
393    pub fn is_timer1break_input(&self) -> bool {
394        *self == COMP1OUTSEL::Timer1breakInput
395    }
396    ///Timer 1 Input capture 1
397    #[inline(always)]
398    pub fn is_timer1input_capture1(&self) -> bool {
399        *self == COMP1OUTSEL::Timer1inputCapture1
400    }
401    ///Timer 1 OCrefclear input
402    #[inline(always)]
403    pub fn is_timer1ocref_clear_input(&self) -> bool {
404        *self == COMP1OUTSEL::Timer1ocrefClearInput
405    }
406    ///Timer 2 input capture 4
407    #[inline(always)]
408    pub fn is_timer2input_capture4(&self) -> bool {
409        *self == COMP1OUTSEL::Timer2inputCapture4
410    }
411    ///Timer 2 OCrefclear input
412    #[inline(always)]
413    pub fn is_timer2ocref_clear_input(&self) -> bool {
414        *self == COMP1OUTSEL::Timer2ocrefClearInput
415    }
416    ///Timer 3 input capture 1
417    #[inline(always)]
418    pub fn is_timer3input_capture1(&self) -> bool {
419        *self == COMP1OUTSEL::Timer3inputCapture1
420    }
421    ///Timer 3 OCrefclear input
422    #[inline(always)]
423    pub fn is_timer3ocref_clear_input(&self) -> bool {
424        *self == COMP1OUTSEL::Timer3ocrefClearInput
425    }
426}
427///Field `COMP1OUTSEL` writer - Comparator 1 output selection
428pub type COMP1OUTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, COMP1OUTSEL, crate::Safe>;
429impl<'a, REG> COMP1OUTSEL_W<'a, REG>
430where
431    REG: crate::Writable + crate::RegisterSpec,
432    REG::Ux: From<u8>,
433{
434    ///No selection
435    #[inline(always)]
436    pub fn no_selection(self) -> &'a mut crate::W<REG> {
437        self.variant(COMP1OUTSEL::NoSelection)
438    }
439    ///Timer 1 break input
440    #[inline(always)]
441    pub fn timer1break_input(self) -> &'a mut crate::W<REG> {
442        self.variant(COMP1OUTSEL::Timer1breakInput)
443    }
444    ///Timer 1 Input capture 1
445    #[inline(always)]
446    pub fn timer1input_capture1(self) -> &'a mut crate::W<REG> {
447        self.variant(COMP1OUTSEL::Timer1inputCapture1)
448    }
449    ///Timer 1 OCrefclear input
450    #[inline(always)]
451    pub fn timer1ocref_clear_input(self) -> &'a mut crate::W<REG> {
452        self.variant(COMP1OUTSEL::Timer1ocrefClearInput)
453    }
454    ///Timer 2 input capture 4
455    #[inline(always)]
456    pub fn timer2input_capture4(self) -> &'a mut crate::W<REG> {
457        self.variant(COMP1OUTSEL::Timer2inputCapture4)
458    }
459    ///Timer 2 OCrefclear input
460    #[inline(always)]
461    pub fn timer2ocref_clear_input(self) -> &'a mut crate::W<REG> {
462        self.variant(COMP1OUTSEL::Timer2ocrefClearInput)
463    }
464    ///Timer 3 input capture 1
465    #[inline(always)]
466    pub fn timer3input_capture1(self) -> &'a mut crate::W<REG> {
467        self.variant(COMP1OUTSEL::Timer3inputCapture1)
468    }
469    ///Timer 3 OCrefclear input
470    #[inline(always)]
471    pub fn timer3ocref_clear_input(self) -> &'a mut crate::W<REG> {
472        self.variant(COMP1OUTSEL::Timer3ocrefClearInput)
473    }
474}
475/**Comparator 1 output polarity
476
477Value on reset: 0*/
478#[cfg_attr(feature = "defmt", derive(defmt::Format))]
479#[derive(Clone, Copy, Debug, PartialEq, Eq)]
480pub enum COMP1POL {
481    ///0: Output is not inverted
482    NotInverted = 0,
483    ///1: Output is inverted
484    Inverted = 1,
485}
486impl From<COMP1POL> for bool {
487    #[inline(always)]
488    fn from(variant: COMP1POL) -> Self {
489        variant as u8 != 0
490    }
491}
492///Field `COMP1POL` reader - Comparator 1 output polarity
493pub type COMP1POL_R = crate::BitReader<COMP1POL>;
494impl COMP1POL_R {
495    ///Get enumerated values variant
496    #[inline(always)]
497    pub const fn variant(&self) -> COMP1POL {
498        match self.bits {
499            false => COMP1POL::NotInverted,
500            true => COMP1POL::Inverted,
501        }
502    }
503    ///Output is not inverted
504    #[inline(always)]
505    pub fn is_not_inverted(&self) -> bool {
506        *self == COMP1POL::NotInverted
507    }
508    ///Output is inverted
509    #[inline(always)]
510    pub fn is_inverted(&self) -> bool {
511        *self == COMP1POL::Inverted
512    }
513}
514///Field `COMP1POL` writer - Comparator 1 output polarity
515pub type COMP1POL_W<'a, REG> = crate::BitWriter<'a, REG, COMP1POL>;
516impl<'a, REG> COMP1POL_W<'a, REG>
517where
518    REG: crate::Writable + crate::RegisterSpec,
519{
520    ///Output is not inverted
521    #[inline(always)]
522    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
523        self.variant(COMP1POL::NotInverted)
524    }
525    ///Output is inverted
526    #[inline(always)]
527    pub fn inverted(self) -> &'a mut crate::W<REG> {
528        self.variant(COMP1POL::Inverted)
529    }
530}
531/**Comparator 1 hysteresis
532
533Value on reset: 0*/
534#[cfg_attr(feature = "defmt", derive(defmt::Format))]
535#[derive(Clone, Copy, Debug, PartialEq, Eq)]
536#[repr(u8)]
537pub enum COMP1HYST {
538    ///0: No hysteresis
539    NoHysteresis = 0,
540    ///1: Low hysteresis
541    LowHysteresis = 1,
542    ///2: Medium hysteresis
543    MediumHysteresis = 2,
544    ///3: High hysteresis
545    HighHysteresis = 3,
546}
547impl From<COMP1HYST> for u8 {
548    #[inline(always)]
549    fn from(variant: COMP1HYST) -> Self {
550        variant as _
551    }
552}
553impl crate::FieldSpec for COMP1HYST {
554    type Ux = u8;
555}
556impl crate::IsEnum for COMP1HYST {}
557///Field `COMP1HYST` reader - Comparator 1 hysteresis
558pub type COMP1HYST_R = crate::FieldReader<COMP1HYST>;
559impl COMP1HYST_R {
560    ///Get enumerated values variant
561    #[inline(always)]
562    pub const fn variant(&self) -> COMP1HYST {
563        match self.bits {
564            0 => COMP1HYST::NoHysteresis,
565            1 => COMP1HYST::LowHysteresis,
566            2 => COMP1HYST::MediumHysteresis,
567            3 => COMP1HYST::HighHysteresis,
568            _ => unreachable!(),
569        }
570    }
571    ///No hysteresis
572    #[inline(always)]
573    pub fn is_no_hysteresis(&self) -> bool {
574        *self == COMP1HYST::NoHysteresis
575    }
576    ///Low hysteresis
577    #[inline(always)]
578    pub fn is_low_hysteresis(&self) -> bool {
579        *self == COMP1HYST::LowHysteresis
580    }
581    ///Medium hysteresis
582    #[inline(always)]
583    pub fn is_medium_hysteresis(&self) -> bool {
584        *self == COMP1HYST::MediumHysteresis
585    }
586    ///High hysteresis
587    #[inline(always)]
588    pub fn is_high_hysteresis(&self) -> bool {
589        *self == COMP1HYST::HighHysteresis
590    }
591}
592///Field `COMP1HYST` writer - Comparator 1 hysteresis
593pub type COMP1HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COMP1HYST, crate::Safe>;
594impl<'a, REG> COMP1HYST_W<'a, REG>
595where
596    REG: crate::Writable + crate::RegisterSpec,
597    REG::Ux: From<u8>,
598{
599    ///No hysteresis
600    #[inline(always)]
601    pub fn no_hysteresis(self) -> &'a mut crate::W<REG> {
602        self.variant(COMP1HYST::NoHysteresis)
603    }
604    ///Low hysteresis
605    #[inline(always)]
606    pub fn low_hysteresis(self) -> &'a mut crate::W<REG> {
607        self.variant(COMP1HYST::LowHysteresis)
608    }
609    ///Medium hysteresis
610    #[inline(always)]
611    pub fn medium_hysteresis(self) -> &'a mut crate::W<REG> {
612        self.variant(COMP1HYST::MediumHysteresis)
613    }
614    ///High hysteresis
615    #[inline(always)]
616    pub fn high_hysteresis(self) -> &'a mut crate::W<REG> {
617        self.variant(COMP1HYST::HighHysteresis)
618    }
619}
620/**Comparator 1 output
621
622Value on reset: 0*/
623#[cfg_attr(feature = "defmt", derive(defmt::Format))]
624#[derive(Clone, Copy, Debug, PartialEq, Eq)]
625pub enum COMP1OUT {
626    ///0: Non-inverting input below inverting input
627    Low = 0,
628    ///1: Non-inverting input above inverting input
629    High = 1,
630}
631impl From<COMP1OUT> for bool {
632    #[inline(always)]
633    fn from(variant: COMP1OUT) -> Self {
634        variant as u8 != 0
635    }
636}
637///Field `COMP1OUT` reader - Comparator 1 output
638pub type COMP1OUT_R = crate::BitReader<COMP1OUT>;
639impl COMP1OUT_R {
640    ///Get enumerated values variant
641    #[inline(always)]
642    pub const fn variant(&self) -> COMP1OUT {
643        match self.bits {
644            false => COMP1OUT::Low,
645            true => COMP1OUT::High,
646        }
647    }
648    ///Non-inverting input below inverting input
649    #[inline(always)]
650    pub fn is_low(&self) -> bool {
651        *self == COMP1OUT::Low
652    }
653    ///Non-inverting input above inverting input
654    #[inline(always)]
655    pub fn is_high(&self) -> bool {
656        *self == COMP1OUT::High
657    }
658}
659/**Comparator 1 lock
660
661Value on reset: 0*/
662#[cfg_attr(feature = "defmt", derive(defmt::Format))]
663#[derive(Clone, Copy, Debug, PartialEq, Eq)]
664pub enum COMP1LOCK {
665    ///0: Comparator 1 CSR bits (CSR\[15:0\]) are read-write
666    Unlocked = 0,
667    ///1: Comparator 1 CSR bits (CSR\[15:0\]) are read-only
668    Locked = 1,
669}
670impl From<COMP1LOCK> for bool {
671    #[inline(always)]
672    fn from(variant: COMP1LOCK) -> Self {
673        variant as u8 != 0
674    }
675}
676///Field `COMP1LOCK` reader - Comparator 1 lock
677pub type COMP1LOCK_R = crate::BitReader<COMP1LOCK>;
678impl COMP1LOCK_R {
679    ///Get enumerated values variant
680    #[inline(always)]
681    pub const fn variant(&self) -> COMP1LOCK {
682        match self.bits {
683            false => COMP1LOCK::Unlocked,
684            true => COMP1LOCK::Locked,
685        }
686    }
687    ///Comparator 1 CSR bits (CSR\[15:0\]) are read-write
688    #[inline(always)]
689    pub fn is_unlocked(&self) -> bool {
690        *self == COMP1LOCK::Unlocked
691    }
692    ///Comparator 1 CSR bits (CSR\[15:0\]) are read-only
693    #[inline(always)]
694    pub fn is_locked(&self) -> bool {
695        *self == COMP1LOCK::Locked
696    }
697}
698///Field `COMP1LOCK` writer - Comparator 1 lock
699pub type COMP1LOCK_W<'a, REG> = crate::BitWriter<'a, REG, COMP1LOCK>;
700impl<'a, REG> COMP1LOCK_W<'a, REG>
701where
702    REG: crate::Writable + crate::RegisterSpec,
703{
704    ///Comparator 1 CSR bits (CSR\[15:0\]) are read-write
705    #[inline(always)]
706    pub fn unlocked(self) -> &'a mut crate::W<REG> {
707        self.variant(COMP1LOCK::Unlocked)
708    }
709    ///Comparator 1 CSR bits (CSR\[15:0\]) are read-only
710    #[inline(always)]
711    pub fn locked(self) -> &'a mut crate::W<REG> {
712        self.variant(COMP1LOCK::Locked)
713    }
714}
715/**Comparator 2 enable
716
717Value on reset: 0*/
718#[cfg_attr(feature = "defmt", derive(defmt::Format))]
719#[derive(Clone, Copy, Debug, PartialEq, Eq)]
720pub enum COMP2EN {
721    ///0: Comparator 2 disabled
722    Disabled = 0,
723    ///1: Comparator 2 enabled
724    Enabled = 1,
725}
726impl From<COMP2EN> for bool {
727    #[inline(always)]
728    fn from(variant: COMP2EN) -> Self {
729        variant as u8 != 0
730    }
731}
732///Field `COMP2EN` reader - Comparator 2 enable
733pub type COMP2EN_R = crate::BitReader<COMP2EN>;
734impl COMP2EN_R {
735    ///Get enumerated values variant
736    #[inline(always)]
737    pub const fn variant(&self) -> COMP2EN {
738        match self.bits {
739            false => COMP2EN::Disabled,
740            true => COMP2EN::Enabled,
741        }
742    }
743    ///Comparator 2 disabled
744    #[inline(always)]
745    pub fn is_disabled(&self) -> bool {
746        *self == COMP2EN::Disabled
747    }
748    ///Comparator 2 enabled
749    #[inline(always)]
750    pub fn is_enabled(&self) -> bool {
751        *self == COMP2EN::Enabled
752    }
753}
754///Field `COMP2EN` writer - Comparator 2 enable
755pub type COMP2EN_W<'a, REG> = crate::BitWriter<'a, REG, COMP2EN>;
756impl<'a, REG> COMP2EN_W<'a, REG>
757where
758    REG: crate::Writable + crate::RegisterSpec,
759{
760    ///Comparator 2 disabled
761    #[inline(always)]
762    pub fn disabled(self) -> &'a mut crate::W<REG> {
763        self.variant(COMP2EN::Disabled)
764    }
765    ///Comparator 2 enabled
766    #[inline(always)]
767    pub fn enabled(self) -> &'a mut crate::W<REG> {
768        self.variant(COMP2EN::Enabled)
769    }
770}
771/**Comparator 2 mode
772
773Value on reset: 0*/
774#[cfg_attr(feature = "defmt", derive(defmt::Format))]
775#[derive(Clone, Copy, Debug, PartialEq, Eq)]
776#[repr(u8)]
777pub enum COMP2MODE {
778    ///0: High speed / full power
779    HighSpeed = 0,
780    ///1: Medium speed / medium power
781    MediumSpeed = 1,
782    ///2: Low speed / low power
783    LowSpeed = 2,
784    ///3: Very-low speed / ultra-low power
785    VeryLowSpeed = 3,
786}
787impl From<COMP2MODE> for u8 {
788    #[inline(always)]
789    fn from(variant: COMP2MODE) -> Self {
790        variant as _
791    }
792}
793impl crate::FieldSpec for COMP2MODE {
794    type Ux = u8;
795}
796impl crate::IsEnum for COMP2MODE {}
797///Field `COMP2MODE` reader - Comparator 2 mode
798pub type COMP2MODE_R = crate::FieldReader<COMP2MODE>;
799impl COMP2MODE_R {
800    ///Get enumerated values variant
801    #[inline(always)]
802    pub const fn variant(&self) -> COMP2MODE {
803        match self.bits {
804            0 => COMP2MODE::HighSpeed,
805            1 => COMP2MODE::MediumSpeed,
806            2 => COMP2MODE::LowSpeed,
807            3 => COMP2MODE::VeryLowSpeed,
808            _ => unreachable!(),
809        }
810    }
811    ///High speed / full power
812    #[inline(always)]
813    pub fn is_high_speed(&self) -> bool {
814        *self == COMP2MODE::HighSpeed
815    }
816    ///Medium speed / medium power
817    #[inline(always)]
818    pub fn is_medium_speed(&self) -> bool {
819        *self == COMP2MODE::MediumSpeed
820    }
821    ///Low speed / low power
822    #[inline(always)]
823    pub fn is_low_speed(&self) -> bool {
824        *self == COMP2MODE::LowSpeed
825    }
826    ///Very-low speed / ultra-low power
827    #[inline(always)]
828    pub fn is_very_low_speed(&self) -> bool {
829        *self == COMP2MODE::VeryLowSpeed
830    }
831}
832///Field `COMP2MODE` writer - Comparator 2 mode
833pub type COMP2MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COMP2MODE, crate::Safe>;
834impl<'a, REG> COMP2MODE_W<'a, REG>
835where
836    REG: crate::Writable + crate::RegisterSpec,
837    REG::Ux: From<u8>,
838{
839    ///High speed / full power
840    #[inline(always)]
841    pub fn high_speed(self) -> &'a mut crate::W<REG> {
842        self.variant(COMP2MODE::HighSpeed)
843    }
844    ///Medium speed / medium power
845    #[inline(always)]
846    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
847        self.variant(COMP2MODE::MediumSpeed)
848    }
849    ///Low speed / low power
850    #[inline(always)]
851    pub fn low_speed(self) -> &'a mut crate::W<REG> {
852        self.variant(COMP2MODE::LowSpeed)
853    }
854    ///Very-low speed / ultra-low power
855    #[inline(always)]
856    pub fn very_low_speed(self) -> &'a mut crate::W<REG> {
857        self.variant(COMP2MODE::VeryLowSpeed)
858    }
859}
860/**Comparator 2 inverting input selection
861
862Value on reset: 0*/
863#[cfg_attr(feature = "defmt", derive(defmt::Format))]
864#[derive(Clone, Copy, Debug, PartialEq, Eq)]
865#[repr(u8)]
866pub enum COMP2INSEL {
867    ///0: 1/4 of VRefint
868    OneQuarterVref = 0,
869    ///1: 1/2 of VRefint
870    OneHalfVref = 1,
871    ///2: 3/4 of VRefint
872    ThreeQuarterVref = 2,
873    ///3: VRefint
874    Vref = 3,
875    ///4: COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
876    Comp2Inm4 = 4,
877    ///5: COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
878    Comp2Inm5 = 5,
879    ///6: COMP1_INM6 (PA2)
880    Comp2Inm6 = 6,
881}
882impl From<COMP2INSEL> for u8 {
883    #[inline(always)]
884    fn from(variant: COMP2INSEL) -> Self {
885        variant as _
886    }
887}
888impl crate::FieldSpec for COMP2INSEL {
889    type Ux = u8;
890}
891impl crate::IsEnum for COMP2INSEL {}
892///Field `COMP2INSEL` reader - Comparator 2 inverting input selection
893pub type COMP2INSEL_R = crate::FieldReader<COMP2INSEL>;
894impl COMP2INSEL_R {
895    ///Get enumerated values variant
896    #[inline(always)]
897    pub const fn variant(&self) -> Option<COMP2INSEL> {
898        match self.bits {
899            0 => Some(COMP2INSEL::OneQuarterVref),
900            1 => Some(COMP2INSEL::OneHalfVref),
901            2 => Some(COMP2INSEL::ThreeQuarterVref),
902            3 => Some(COMP2INSEL::Vref),
903            4 => Some(COMP2INSEL::Comp2Inm4),
904            5 => Some(COMP2INSEL::Comp2Inm5),
905            6 => Some(COMP2INSEL::Comp2Inm6),
906            _ => None,
907        }
908    }
909    ///1/4 of VRefint
910    #[inline(always)]
911    pub fn is_one_quarter_vref(&self) -> bool {
912        *self == COMP2INSEL::OneQuarterVref
913    }
914    ///1/2 of VRefint
915    #[inline(always)]
916    pub fn is_one_half_vref(&self) -> bool {
917        *self == COMP2INSEL::OneHalfVref
918    }
919    ///3/4 of VRefint
920    #[inline(always)]
921    pub fn is_three_quarter_vref(&self) -> bool {
922        *self == COMP2INSEL::ThreeQuarterVref
923    }
924    ///VRefint
925    #[inline(always)]
926    pub fn is_vref(&self) -> bool {
927        *self == COMP2INSEL::Vref
928    }
929    ///COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
930    #[inline(always)]
931    pub fn is_comp2_inm4(&self) -> bool {
932        *self == COMP2INSEL::Comp2Inm4
933    }
934    ///COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
935    #[inline(always)]
936    pub fn is_comp2_inm5(&self) -> bool {
937        *self == COMP2INSEL::Comp2Inm5
938    }
939    ///COMP1_INM6 (PA2)
940    #[inline(always)]
941    pub fn is_comp2_inm6(&self) -> bool {
942        *self == COMP2INSEL::Comp2Inm6
943    }
944}
945///Field `COMP2INSEL` writer - Comparator 2 inverting input selection
946pub type COMP2INSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, COMP2INSEL>;
947impl<'a, REG> COMP2INSEL_W<'a, REG>
948where
949    REG: crate::Writable + crate::RegisterSpec,
950    REG::Ux: From<u8>,
951{
952    ///1/4 of VRefint
953    #[inline(always)]
954    pub fn one_quarter_vref(self) -> &'a mut crate::W<REG> {
955        self.variant(COMP2INSEL::OneQuarterVref)
956    }
957    ///1/2 of VRefint
958    #[inline(always)]
959    pub fn one_half_vref(self) -> &'a mut crate::W<REG> {
960        self.variant(COMP2INSEL::OneHalfVref)
961    }
962    ///3/4 of VRefint
963    #[inline(always)]
964    pub fn three_quarter_vref(self) -> &'a mut crate::W<REG> {
965        self.variant(COMP2INSEL::ThreeQuarterVref)
966    }
967    ///VRefint
968    #[inline(always)]
969    pub fn vref(self) -> &'a mut crate::W<REG> {
970        self.variant(COMP2INSEL::Vref)
971    }
972    ///COMP1_INM4 (PA4 with DAC_OUT1 if enabled)
973    #[inline(always)]
974    pub fn comp2_inm4(self) -> &'a mut crate::W<REG> {
975        self.variant(COMP2INSEL::Comp2Inm4)
976    }
977    ///COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)
978    #[inline(always)]
979    pub fn comp2_inm5(self) -> &'a mut crate::W<REG> {
980        self.variant(COMP2INSEL::Comp2Inm5)
981    }
982    ///COMP1_INM6 (PA2)
983    #[inline(always)]
984    pub fn comp2_inm6(self) -> &'a mut crate::W<REG> {
985        self.variant(COMP2INSEL::Comp2Inm6)
986    }
987}
988/**Window mode enable
989
990Value on reset: 0*/
991#[cfg_attr(feature = "defmt", derive(defmt::Format))]
992#[derive(Clone, Copy, Debug, PartialEq, Eq)]
993pub enum WNDWEN {
994    ///0: Window mode disabled
995    Disabled = 0,
996    ///1: Window mode enabled
997    Enabled = 1,
998}
999impl From<WNDWEN> for bool {
1000    #[inline(always)]
1001    fn from(variant: WNDWEN) -> Self {
1002        variant as u8 != 0
1003    }
1004}
1005///Field `WNDWEN` reader - Window mode enable
1006pub type WNDWEN_R = crate::BitReader<WNDWEN>;
1007impl WNDWEN_R {
1008    ///Get enumerated values variant
1009    #[inline(always)]
1010    pub const fn variant(&self) -> WNDWEN {
1011        match self.bits {
1012            false => WNDWEN::Disabled,
1013            true => WNDWEN::Enabled,
1014        }
1015    }
1016    ///Window mode disabled
1017    #[inline(always)]
1018    pub fn is_disabled(&self) -> bool {
1019        *self == WNDWEN::Disabled
1020    }
1021    ///Window mode enabled
1022    #[inline(always)]
1023    pub fn is_enabled(&self) -> bool {
1024        *self == WNDWEN::Enabled
1025    }
1026}
1027///Field `WNDWEN` writer - Window mode enable
1028pub type WNDWEN_W<'a, REG> = crate::BitWriter<'a, REG, WNDWEN>;
1029impl<'a, REG> WNDWEN_W<'a, REG>
1030where
1031    REG: crate::Writable + crate::RegisterSpec,
1032{
1033    ///Window mode disabled
1034    #[inline(always)]
1035    pub fn disabled(self) -> &'a mut crate::W<REG> {
1036        self.variant(WNDWEN::Disabled)
1037    }
1038    ///Window mode enabled
1039    #[inline(always)]
1040    pub fn enabled(self) -> &'a mut crate::W<REG> {
1041        self.variant(WNDWEN::Enabled)
1042    }
1043}
1044/**Comparator 2 output selection
1045
1046Value on reset: 0*/
1047#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1048#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1049#[repr(u8)]
1050pub enum COMP2OUTSEL {
1051    ///0: No selection
1052    NoSelection = 0,
1053    ///1: Timer 1 break input
1054    Timer1breakInput = 1,
1055    ///2: Timer 1 Input capture 1
1056    Timer1inputCapture1 = 2,
1057    ///3: Timer 1 OCrefclear input
1058    Timer1ocrefClearInput = 3,
1059    ///4: Timer 2 input capture 4
1060    Timer2inputCapture4 = 4,
1061    ///5: Timer 2 OCrefclear input
1062    Timer2ocrefClearInput = 5,
1063    ///6: Timer 3 input capture 1
1064    Timer3inputCapture1 = 6,
1065    ///7: Timer 3 OCrefclear input
1066    Timer3ocrefClearInput = 7,
1067}
1068impl From<COMP2OUTSEL> for u8 {
1069    #[inline(always)]
1070    fn from(variant: COMP2OUTSEL) -> Self {
1071        variant as _
1072    }
1073}
1074impl crate::FieldSpec for COMP2OUTSEL {
1075    type Ux = u8;
1076}
1077impl crate::IsEnum for COMP2OUTSEL {}
1078///Field `COMP2OUTSEL` reader - Comparator 2 output selection
1079pub type COMP2OUTSEL_R = crate::FieldReader<COMP2OUTSEL>;
1080impl COMP2OUTSEL_R {
1081    ///Get enumerated values variant
1082    #[inline(always)]
1083    pub const fn variant(&self) -> COMP2OUTSEL {
1084        match self.bits {
1085            0 => COMP2OUTSEL::NoSelection,
1086            1 => COMP2OUTSEL::Timer1breakInput,
1087            2 => COMP2OUTSEL::Timer1inputCapture1,
1088            3 => COMP2OUTSEL::Timer1ocrefClearInput,
1089            4 => COMP2OUTSEL::Timer2inputCapture4,
1090            5 => COMP2OUTSEL::Timer2ocrefClearInput,
1091            6 => COMP2OUTSEL::Timer3inputCapture1,
1092            7 => COMP2OUTSEL::Timer3ocrefClearInput,
1093            _ => unreachable!(),
1094        }
1095    }
1096    ///No selection
1097    #[inline(always)]
1098    pub fn is_no_selection(&self) -> bool {
1099        *self == COMP2OUTSEL::NoSelection
1100    }
1101    ///Timer 1 break input
1102    #[inline(always)]
1103    pub fn is_timer1break_input(&self) -> bool {
1104        *self == COMP2OUTSEL::Timer1breakInput
1105    }
1106    ///Timer 1 Input capture 1
1107    #[inline(always)]
1108    pub fn is_timer1input_capture1(&self) -> bool {
1109        *self == COMP2OUTSEL::Timer1inputCapture1
1110    }
1111    ///Timer 1 OCrefclear input
1112    #[inline(always)]
1113    pub fn is_timer1ocref_clear_input(&self) -> bool {
1114        *self == COMP2OUTSEL::Timer1ocrefClearInput
1115    }
1116    ///Timer 2 input capture 4
1117    #[inline(always)]
1118    pub fn is_timer2input_capture4(&self) -> bool {
1119        *self == COMP2OUTSEL::Timer2inputCapture4
1120    }
1121    ///Timer 2 OCrefclear input
1122    #[inline(always)]
1123    pub fn is_timer2ocref_clear_input(&self) -> bool {
1124        *self == COMP2OUTSEL::Timer2ocrefClearInput
1125    }
1126    ///Timer 3 input capture 1
1127    #[inline(always)]
1128    pub fn is_timer3input_capture1(&self) -> bool {
1129        *self == COMP2OUTSEL::Timer3inputCapture1
1130    }
1131    ///Timer 3 OCrefclear input
1132    #[inline(always)]
1133    pub fn is_timer3ocref_clear_input(&self) -> bool {
1134        *self == COMP2OUTSEL::Timer3ocrefClearInput
1135    }
1136}
1137///Field `COMP2OUTSEL` writer - Comparator 2 output selection
1138pub type COMP2OUTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, COMP2OUTSEL, crate::Safe>;
1139impl<'a, REG> COMP2OUTSEL_W<'a, REG>
1140where
1141    REG: crate::Writable + crate::RegisterSpec,
1142    REG::Ux: From<u8>,
1143{
1144    ///No selection
1145    #[inline(always)]
1146    pub fn no_selection(self) -> &'a mut crate::W<REG> {
1147        self.variant(COMP2OUTSEL::NoSelection)
1148    }
1149    ///Timer 1 break input
1150    #[inline(always)]
1151    pub fn timer1break_input(self) -> &'a mut crate::W<REG> {
1152        self.variant(COMP2OUTSEL::Timer1breakInput)
1153    }
1154    ///Timer 1 Input capture 1
1155    #[inline(always)]
1156    pub fn timer1input_capture1(self) -> &'a mut crate::W<REG> {
1157        self.variant(COMP2OUTSEL::Timer1inputCapture1)
1158    }
1159    ///Timer 1 OCrefclear input
1160    #[inline(always)]
1161    pub fn timer1ocref_clear_input(self) -> &'a mut crate::W<REG> {
1162        self.variant(COMP2OUTSEL::Timer1ocrefClearInput)
1163    }
1164    ///Timer 2 input capture 4
1165    #[inline(always)]
1166    pub fn timer2input_capture4(self) -> &'a mut crate::W<REG> {
1167        self.variant(COMP2OUTSEL::Timer2inputCapture4)
1168    }
1169    ///Timer 2 OCrefclear input
1170    #[inline(always)]
1171    pub fn timer2ocref_clear_input(self) -> &'a mut crate::W<REG> {
1172        self.variant(COMP2OUTSEL::Timer2ocrefClearInput)
1173    }
1174    ///Timer 3 input capture 1
1175    #[inline(always)]
1176    pub fn timer3input_capture1(self) -> &'a mut crate::W<REG> {
1177        self.variant(COMP2OUTSEL::Timer3inputCapture1)
1178    }
1179    ///Timer 3 OCrefclear input
1180    #[inline(always)]
1181    pub fn timer3ocref_clear_input(self) -> &'a mut crate::W<REG> {
1182        self.variant(COMP2OUTSEL::Timer3ocrefClearInput)
1183    }
1184}
1185/**Comparator 2 output polarity
1186
1187Value on reset: 0*/
1188#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1189#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1190pub enum COMP2POL {
1191    ///0: Output is not inverted
1192    NotInverted = 0,
1193    ///1: Output is inverted
1194    Inverted = 1,
1195}
1196impl From<COMP2POL> for bool {
1197    #[inline(always)]
1198    fn from(variant: COMP2POL) -> Self {
1199        variant as u8 != 0
1200    }
1201}
1202///Field `COMP2POL` reader - Comparator 2 output polarity
1203pub type COMP2POL_R = crate::BitReader<COMP2POL>;
1204impl COMP2POL_R {
1205    ///Get enumerated values variant
1206    #[inline(always)]
1207    pub const fn variant(&self) -> COMP2POL {
1208        match self.bits {
1209            false => COMP2POL::NotInverted,
1210            true => COMP2POL::Inverted,
1211        }
1212    }
1213    ///Output is not inverted
1214    #[inline(always)]
1215    pub fn is_not_inverted(&self) -> bool {
1216        *self == COMP2POL::NotInverted
1217    }
1218    ///Output is inverted
1219    #[inline(always)]
1220    pub fn is_inverted(&self) -> bool {
1221        *self == COMP2POL::Inverted
1222    }
1223}
1224///Field `COMP2POL` writer - Comparator 2 output polarity
1225pub type COMP2POL_W<'a, REG> = crate::BitWriter<'a, REG, COMP2POL>;
1226impl<'a, REG> COMP2POL_W<'a, REG>
1227where
1228    REG: crate::Writable + crate::RegisterSpec,
1229{
1230    ///Output is not inverted
1231    #[inline(always)]
1232    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
1233        self.variant(COMP2POL::NotInverted)
1234    }
1235    ///Output is inverted
1236    #[inline(always)]
1237    pub fn inverted(self) -> &'a mut crate::W<REG> {
1238        self.variant(COMP2POL::Inverted)
1239    }
1240}
1241/**Comparator 2 hysteresis
1242
1243Value on reset: 0*/
1244#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1245#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1246#[repr(u8)]
1247pub enum COMP2HYST {
1248    ///0: No hysteresis
1249    NoHysteresis = 0,
1250    ///1: Low hysteresis
1251    LowHysteresis = 1,
1252    ///2: Medium hysteresis
1253    MediumHysteresis = 2,
1254    ///3: High hysteresis
1255    HighHysteresis = 3,
1256}
1257impl From<COMP2HYST> for u8 {
1258    #[inline(always)]
1259    fn from(variant: COMP2HYST) -> Self {
1260        variant as _
1261    }
1262}
1263impl crate::FieldSpec for COMP2HYST {
1264    type Ux = u8;
1265}
1266impl crate::IsEnum for COMP2HYST {}
1267///Field `COMP2HYST` reader - Comparator 2 hysteresis
1268pub type COMP2HYST_R = crate::FieldReader<COMP2HYST>;
1269impl COMP2HYST_R {
1270    ///Get enumerated values variant
1271    #[inline(always)]
1272    pub const fn variant(&self) -> COMP2HYST {
1273        match self.bits {
1274            0 => COMP2HYST::NoHysteresis,
1275            1 => COMP2HYST::LowHysteresis,
1276            2 => COMP2HYST::MediumHysteresis,
1277            3 => COMP2HYST::HighHysteresis,
1278            _ => unreachable!(),
1279        }
1280    }
1281    ///No hysteresis
1282    #[inline(always)]
1283    pub fn is_no_hysteresis(&self) -> bool {
1284        *self == COMP2HYST::NoHysteresis
1285    }
1286    ///Low hysteresis
1287    #[inline(always)]
1288    pub fn is_low_hysteresis(&self) -> bool {
1289        *self == COMP2HYST::LowHysteresis
1290    }
1291    ///Medium hysteresis
1292    #[inline(always)]
1293    pub fn is_medium_hysteresis(&self) -> bool {
1294        *self == COMP2HYST::MediumHysteresis
1295    }
1296    ///High hysteresis
1297    #[inline(always)]
1298    pub fn is_high_hysteresis(&self) -> bool {
1299        *self == COMP2HYST::HighHysteresis
1300    }
1301}
1302///Field `COMP2HYST` writer - Comparator 2 hysteresis
1303pub type COMP2HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2, COMP2HYST, crate::Safe>;
1304impl<'a, REG> COMP2HYST_W<'a, REG>
1305where
1306    REG: crate::Writable + crate::RegisterSpec,
1307    REG::Ux: From<u8>,
1308{
1309    ///No hysteresis
1310    #[inline(always)]
1311    pub fn no_hysteresis(self) -> &'a mut crate::W<REG> {
1312        self.variant(COMP2HYST::NoHysteresis)
1313    }
1314    ///Low hysteresis
1315    #[inline(always)]
1316    pub fn low_hysteresis(self) -> &'a mut crate::W<REG> {
1317        self.variant(COMP2HYST::LowHysteresis)
1318    }
1319    ///Medium hysteresis
1320    #[inline(always)]
1321    pub fn medium_hysteresis(self) -> &'a mut crate::W<REG> {
1322        self.variant(COMP2HYST::MediumHysteresis)
1323    }
1324    ///High hysteresis
1325    #[inline(always)]
1326    pub fn high_hysteresis(self) -> &'a mut crate::W<REG> {
1327        self.variant(COMP2HYST::HighHysteresis)
1328    }
1329}
1330/**Comparator 2 output
1331
1332Value on reset: 0*/
1333#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1335pub enum COMP2OUT {
1336    ///0: Non-inverting input below inverting input
1337    Low = 0,
1338    ///1: Non-inverting input above inverting input
1339    High = 1,
1340}
1341impl From<COMP2OUT> for bool {
1342    #[inline(always)]
1343    fn from(variant: COMP2OUT) -> Self {
1344        variant as u8 != 0
1345    }
1346}
1347///Field `COMP2OUT` reader - Comparator 2 output
1348pub type COMP2OUT_R = crate::BitReader<COMP2OUT>;
1349impl COMP2OUT_R {
1350    ///Get enumerated values variant
1351    #[inline(always)]
1352    pub const fn variant(&self) -> COMP2OUT {
1353        match self.bits {
1354            false => COMP2OUT::Low,
1355            true => COMP2OUT::High,
1356        }
1357    }
1358    ///Non-inverting input below inverting input
1359    #[inline(always)]
1360    pub fn is_low(&self) -> bool {
1361        *self == COMP2OUT::Low
1362    }
1363    ///Non-inverting input above inverting input
1364    #[inline(always)]
1365    pub fn is_high(&self) -> bool {
1366        *self == COMP2OUT::High
1367    }
1368}
1369/**Comparator 2 lock
1370
1371Value on reset: 0*/
1372#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1373#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1374pub enum COMP2LOCK {
1375    ///0: Comparator 2 CSR bits (CSR\[31:16\]) are read-write
1376    Unlocked = 0,
1377    ///1: Comparator 2 CSR bits (CSR\[31:16\]) are read-only
1378    Locked = 1,
1379}
1380impl From<COMP2LOCK> for bool {
1381    #[inline(always)]
1382    fn from(variant: COMP2LOCK) -> Self {
1383        variant as u8 != 0
1384    }
1385}
1386///Field `COMP2LOCK` reader - Comparator 2 lock
1387pub type COMP2LOCK_R = crate::BitReader<COMP2LOCK>;
1388impl COMP2LOCK_R {
1389    ///Get enumerated values variant
1390    #[inline(always)]
1391    pub const fn variant(&self) -> COMP2LOCK {
1392        match self.bits {
1393            false => COMP2LOCK::Unlocked,
1394            true => COMP2LOCK::Locked,
1395        }
1396    }
1397    ///Comparator 2 CSR bits (CSR\[31:16\]) are read-write
1398    #[inline(always)]
1399    pub fn is_unlocked(&self) -> bool {
1400        *self == COMP2LOCK::Unlocked
1401    }
1402    ///Comparator 2 CSR bits (CSR\[31:16\]) are read-only
1403    #[inline(always)]
1404    pub fn is_locked(&self) -> bool {
1405        *self == COMP2LOCK::Locked
1406    }
1407}
1408///Field `COMP2LOCK` writer - Comparator 2 lock
1409pub type COMP2LOCK_W<'a, REG> = crate::BitWriter<'a, REG, COMP2LOCK>;
1410impl<'a, REG> COMP2LOCK_W<'a, REG>
1411where
1412    REG: crate::Writable + crate::RegisterSpec,
1413{
1414    ///Comparator 2 CSR bits (CSR\[31:16\]) are read-write
1415    #[inline(always)]
1416    pub fn unlocked(self) -> &'a mut crate::W<REG> {
1417        self.variant(COMP2LOCK::Unlocked)
1418    }
1419    ///Comparator 2 CSR bits (CSR\[31:16\]) are read-only
1420    #[inline(always)]
1421    pub fn locked(self) -> &'a mut crate::W<REG> {
1422        self.variant(COMP2LOCK::Locked)
1423    }
1424}
1425impl R {
1426    ///Bit 0 - Comparator 1 enable
1427    #[inline(always)]
1428    pub fn comp1en(&self) -> COMP1EN_R {
1429        COMP1EN_R::new((self.bits & 1) != 0)
1430    }
1431    ///Bit 1 - Comparator 1 non inverting input DAC switch
1432    #[inline(always)]
1433    pub fn comp1sw1(&self) -> COMP1SW1_R {
1434        COMP1SW1_R::new(((self.bits >> 1) & 1) != 0)
1435    }
1436    ///Bits 2:3 - Comparator 1 mode
1437    #[inline(always)]
1438    pub fn comp1mode(&self) -> COMP1MODE_R {
1439        COMP1MODE_R::new(((self.bits >> 2) & 3) as u8)
1440    }
1441    ///Bits 4:6 - Comparator 1 inverting input selection
1442    #[inline(always)]
1443    pub fn comp1insel(&self) -> COMP1INSEL_R {
1444        COMP1INSEL_R::new(((self.bits >> 4) & 7) as u8)
1445    }
1446    ///Bits 8:10 - Comparator 1 output selection
1447    #[inline(always)]
1448    pub fn comp1outsel(&self) -> COMP1OUTSEL_R {
1449        COMP1OUTSEL_R::new(((self.bits >> 8) & 7) as u8)
1450    }
1451    ///Bit 11 - Comparator 1 output polarity
1452    #[inline(always)]
1453    pub fn comp1pol(&self) -> COMP1POL_R {
1454        COMP1POL_R::new(((self.bits >> 11) & 1) != 0)
1455    }
1456    ///Bits 12:13 - Comparator 1 hysteresis
1457    #[inline(always)]
1458    pub fn comp1hyst(&self) -> COMP1HYST_R {
1459        COMP1HYST_R::new(((self.bits >> 12) & 3) as u8)
1460    }
1461    ///Bit 14 - Comparator 1 output
1462    #[inline(always)]
1463    pub fn comp1out(&self) -> COMP1OUT_R {
1464        COMP1OUT_R::new(((self.bits >> 14) & 1) != 0)
1465    }
1466    ///Bit 15 - Comparator 1 lock
1467    #[inline(always)]
1468    pub fn comp1lock(&self) -> COMP1LOCK_R {
1469        COMP1LOCK_R::new(((self.bits >> 15) & 1) != 0)
1470    }
1471    ///Bit 16 - Comparator 2 enable
1472    #[inline(always)]
1473    pub fn comp2en(&self) -> COMP2EN_R {
1474        COMP2EN_R::new(((self.bits >> 16) & 1) != 0)
1475    }
1476    ///Bits 18:19 - Comparator 2 mode
1477    #[inline(always)]
1478    pub fn comp2mode(&self) -> COMP2MODE_R {
1479        COMP2MODE_R::new(((self.bits >> 18) & 3) as u8)
1480    }
1481    ///Bits 20:22 - Comparator 2 inverting input selection
1482    #[inline(always)]
1483    pub fn comp2insel(&self) -> COMP2INSEL_R {
1484        COMP2INSEL_R::new(((self.bits >> 20) & 7) as u8)
1485    }
1486    ///Bit 23 - Window mode enable
1487    #[inline(always)]
1488    pub fn wndwen(&self) -> WNDWEN_R {
1489        WNDWEN_R::new(((self.bits >> 23) & 1) != 0)
1490    }
1491    ///Bits 24:26 - Comparator 2 output selection
1492    #[inline(always)]
1493    pub fn comp2outsel(&self) -> COMP2OUTSEL_R {
1494        COMP2OUTSEL_R::new(((self.bits >> 24) & 7) as u8)
1495    }
1496    ///Bit 27 - Comparator 2 output polarity
1497    #[inline(always)]
1498    pub fn comp2pol(&self) -> COMP2POL_R {
1499        COMP2POL_R::new(((self.bits >> 27) & 1) != 0)
1500    }
1501    ///Bits 28:29 - Comparator 2 hysteresis
1502    #[inline(always)]
1503    pub fn comp2hyst(&self) -> COMP2HYST_R {
1504        COMP2HYST_R::new(((self.bits >> 28) & 3) as u8)
1505    }
1506    ///Bit 30 - Comparator 2 output
1507    #[inline(always)]
1508    pub fn comp2out(&self) -> COMP2OUT_R {
1509        COMP2OUT_R::new(((self.bits >> 30) & 1) != 0)
1510    }
1511    ///Bit 31 - Comparator 2 lock
1512    #[inline(always)]
1513    pub fn comp2lock(&self) -> COMP2LOCK_R {
1514        COMP2LOCK_R::new(((self.bits >> 31) & 1) != 0)
1515    }
1516}
1517impl core::fmt::Debug for R {
1518    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1519        f.debug_struct("CSR")
1520            .field("comp1en", &self.comp1en())
1521            .field("comp1mode", &self.comp1mode())
1522            .field("comp1insel", &self.comp1insel())
1523            .field("comp1outsel", &self.comp1outsel())
1524            .field("comp1pol", &self.comp1pol())
1525            .field("comp1hyst", &self.comp1hyst())
1526            .field("comp1out", &self.comp1out())
1527            .field("comp1lock", &self.comp1lock())
1528            .field("comp2en", &self.comp2en())
1529            .field("comp2mode", &self.comp2mode())
1530            .field("comp2insel", &self.comp2insel())
1531            .field("wndwen", &self.wndwen())
1532            .field("comp2outsel", &self.comp2outsel())
1533            .field("comp2pol", &self.comp2pol())
1534            .field("comp2hyst", &self.comp2hyst())
1535            .field("comp2out", &self.comp2out())
1536            .field("comp2lock", &self.comp2lock())
1537            .field("comp1sw1", &self.comp1sw1())
1538            .finish()
1539    }
1540}
1541impl W {
1542    ///Bit 0 - Comparator 1 enable
1543    #[inline(always)]
1544    pub fn comp1en(&mut self) -> COMP1EN_W<CSRrs> {
1545        COMP1EN_W::new(self, 0)
1546    }
1547    ///Bit 1 - Comparator 1 non inverting input DAC switch
1548    #[inline(always)]
1549    pub fn comp1sw1(&mut self) -> COMP1SW1_W<CSRrs> {
1550        COMP1SW1_W::new(self, 1)
1551    }
1552    ///Bits 2:3 - Comparator 1 mode
1553    #[inline(always)]
1554    pub fn comp1mode(&mut self) -> COMP1MODE_W<CSRrs> {
1555        COMP1MODE_W::new(self, 2)
1556    }
1557    ///Bits 4:6 - Comparator 1 inverting input selection
1558    #[inline(always)]
1559    pub fn comp1insel(&mut self) -> COMP1INSEL_W<CSRrs> {
1560        COMP1INSEL_W::new(self, 4)
1561    }
1562    ///Bits 8:10 - Comparator 1 output selection
1563    #[inline(always)]
1564    pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<CSRrs> {
1565        COMP1OUTSEL_W::new(self, 8)
1566    }
1567    ///Bit 11 - Comparator 1 output polarity
1568    #[inline(always)]
1569    pub fn comp1pol(&mut self) -> COMP1POL_W<CSRrs> {
1570        COMP1POL_W::new(self, 11)
1571    }
1572    ///Bits 12:13 - Comparator 1 hysteresis
1573    #[inline(always)]
1574    pub fn comp1hyst(&mut self) -> COMP1HYST_W<CSRrs> {
1575        COMP1HYST_W::new(self, 12)
1576    }
1577    ///Bit 15 - Comparator 1 lock
1578    #[inline(always)]
1579    pub fn comp1lock(&mut self) -> COMP1LOCK_W<CSRrs> {
1580        COMP1LOCK_W::new(self, 15)
1581    }
1582    ///Bit 16 - Comparator 2 enable
1583    #[inline(always)]
1584    pub fn comp2en(&mut self) -> COMP2EN_W<CSRrs> {
1585        COMP2EN_W::new(self, 16)
1586    }
1587    ///Bits 18:19 - Comparator 2 mode
1588    #[inline(always)]
1589    pub fn comp2mode(&mut self) -> COMP2MODE_W<CSRrs> {
1590        COMP2MODE_W::new(self, 18)
1591    }
1592    ///Bits 20:22 - Comparator 2 inverting input selection
1593    #[inline(always)]
1594    pub fn comp2insel(&mut self) -> COMP2INSEL_W<CSRrs> {
1595        COMP2INSEL_W::new(self, 20)
1596    }
1597    ///Bit 23 - Window mode enable
1598    #[inline(always)]
1599    pub fn wndwen(&mut self) -> WNDWEN_W<CSRrs> {
1600        WNDWEN_W::new(self, 23)
1601    }
1602    ///Bits 24:26 - Comparator 2 output selection
1603    #[inline(always)]
1604    pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<CSRrs> {
1605        COMP2OUTSEL_W::new(self, 24)
1606    }
1607    ///Bit 27 - Comparator 2 output polarity
1608    #[inline(always)]
1609    pub fn comp2pol(&mut self) -> COMP2POL_W<CSRrs> {
1610        COMP2POL_W::new(self, 27)
1611    }
1612    ///Bits 28:29 - Comparator 2 hysteresis
1613    #[inline(always)]
1614    pub fn comp2hyst(&mut self) -> COMP2HYST_W<CSRrs> {
1615        COMP2HYST_W::new(self, 28)
1616    }
1617    ///Bit 31 - Comparator 2 lock
1618    #[inline(always)]
1619    pub fn comp2lock(&mut self) -> COMP2LOCK_W<CSRrs> {
1620        COMP2LOCK_W::new(self, 31)
1621    }
1622}
1623/**control and status register
1624
1625You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1626
1627See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#COMP:CSR)*/
1628pub struct CSRrs;
1629impl crate::RegisterSpec for CSRrs {
1630    type Ux = u32;
1631}
1632///`read()` method returns [`csr::R`](R) reader structure
1633impl crate::Readable for CSRrs {}
1634///`write(|w| ..)` method takes [`csr::W`](W) writer structure
1635impl crate::Writable for CSRrs {
1636    type Safety = crate::Unsafe;
1637}
1638///`reset()` method sets CSR to value 0
1639impl crate::Resettable for CSRrs {}
stm32f0/stm32f0x2/comp/csr.rs

stm32f0/stm32f0x2/comp/
csr.rs
