stm32f0/stm32f0x1/usb/
cntr.rs

1///Register `CNTR` reader
2pub type R = crate::R<CNTRrs>;
3///Register `CNTR` writer
4pub type W = crate::W<CNTRrs>;
5/**Force USB Reset
6
7Value on reset: 1*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum FRES {
11    ///0: Clear USB reset
12    NoReset = 0,
13    ///1: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
14    Reset = 1,
15}
16impl From<FRES> for bool {
17    #[inline(always)]
18    fn from(variant: FRES) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `FRES` reader - Force USB Reset
23pub type FRES_R = crate::BitReader<FRES>;
24impl FRES_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> FRES {
28        match self.bits {
29            false => FRES::NoReset,
30            true => FRES::Reset,
31        }
32    }
33    ///Clear USB reset
34    #[inline(always)]
35    pub fn is_no_reset(&self) -> bool {
36        *self == FRES::NoReset
37    }
38    ///Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
39    #[inline(always)]
40    pub fn is_reset(&self) -> bool {
41        *self == FRES::Reset
42    }
43}
44///Field `FRES` writer - Force USB Reset
45pub type FRES_W<'a, REG> = crate::BitWriter<'a, REG, FRES>;
46impl<'a, REG> FRES_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Clear USB reset
51    #[inline(always)]
52    pub fn no_reset(self) -> &'a mut crate::W<REG> {
53        self.variant(FRES::NoReset)
54    }
55    ///Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
56    #[inline(always)]
57    pub fn reset(self) -> &'a mut crate::W<REG> {
58        self.variant(FRES::Reset)
59    }
60}
61/**Power down
62
63Value on reset: 1*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum PDWN {
67    ///0: No power down
68    Disabled = 0,
69    ///1: Enter power down mode
70    Enabled = 1,
71}
72impl From<PDWN> for bool {
73    #[inline(always)]
74    fn from(variant: PDWN) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `PDWN` reader - Power down
79pub type PDWN_R = crate::BitReader<PDWN>;
80impl PDWN_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> PDWN {
84        match self.bits {
85            false => PDWN::Disabled,
86            true => PDWN::Enabled,
87        }
88    }
89    ///No power down
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == PDWN::Disabled
93    }
94    ///Enter power down mode
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == PDWN::Enabled
98    }
99}
100///Field `PDWN` writer - Power down
101pub type PDWN_W<'a, REG> = crate::BitWriter<'a, REG, PDWN>;
102impl<'a, REG> PDWN_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///No power down
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(PDWN::Disabled)
110    }
111    ///Enter power down mode
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(PDWN::Enabled)
115    }
116}
117/**Low-power mode
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum LPMODE {
123    ///0: No low-power mode
124    Disabled = 0,
125    ///1: Enter low-power mode
126    Enabled = 1,
127}
128impl From<LPMODE> for bool {
129    #[inline(always)]
130    fn from(variant: LPMODE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `LPMODE` reader - Low-power mode
135pub type LPMODE_R = crate::BitReader<LPMODE>;
136impl LPMODE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> LPMODE {
140        match self.bits {
141            false => LPMODE::Disabled,
142            true => LPMODE::Enabled,
143        }
144    }
145    ///No low-power mode
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == LPMODE::Disabled
149    }
150    ///Enter low-power mode
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == LPMODE::Enabled
154    }
155}
156///Field `LPMODE` writer - Low-power mode
157pub type LPMODE_W<'a, REG> = crate::BitWriter<'a, REG, LPMODE>;
158impl<'a, REG> LPMODE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///No low-power mode
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(LPMODE::Disabled)
166    }
167    ///Enter low-power mode
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(LPMODE::Enabled)
171    }
172}
173/**Force suspend
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum FSUSP {
179    ///0: No effect
180    NoEffect = 0,
181    ///1: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
182    Suspend = 1,
183}
184impl From<FSUSP> for bool {
185    #[inline(always)]
186    fn from(variant: FSUSP) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `FSUSP` reader - Force suspend
191pub type FSUSP_R = crate::BitReader<FSUSP>;
192impl FSUSP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> FSUSP {
196        match self.bits {
197            false => FSUSP::NoEffect,
198            true => FSUSP::Suspend,
199        }
200    }
201    ///No effect
202    #[inline(always)]
203    pub fn is_no_effect(&self) -> bool {
204        *self == FSUSP::NoEffect
205    }
206    ///Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
207    #[inline(always)]
208    pub fn is_suspend(&self) -> bool {
209        *self == FSUSP::Suspend
210    }
211}
212///Field `FSUSP` writer - Force suspend
213pub type FSUSP_W<'a, REG> = crate::BitWriter<'a, REG, FSUSP>;
214impl<'a, REG> FSUSP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///No effect
219    #[inline(always)]
220    pub fn no_effect(self) -> &'a mut crate::W<REG> {
221        self.variant(FSUSP::NoEffect)
222    }
223    ///Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
224    #[inline(always)]
225    pub fn suspend(self) -> &'a mut crate::W<REG> {
226        self.variant(FSUSP::Suspend)
227    }
228}
229/**Resume request
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum RESUME {
235    ///1: Resume requested
236    Requested = 1,
237}
238impl From<RESUME> for bool {
239    #[inline(always)]
240    fn from(variant: RESUME) -> Self {
241        variant as u8 != 0
242    }
243}
244///Field `RESUME` reader - Resume request
245pub type RESUME_R = crate::BitReader<RESUME>;
246impl RESUME_R {
247    ///Get enumerated values variant
248    #[inline(always)]
249    pub const fn variant(&self) -> Option<RESUME> {
250        match self.bits {
251            true => Some(RESUME::Requested),
252            _ => None,
253        }
254    }
255    ///Resume requested
256    #[inline(always)]
257    pub fn is_requested(&self) -> bool {
258        *self == RESUME::Requested
259    }
260}
261///Field `RESUME` writer - Resume request
262pub type RESUME_W<'a, REG> = crate::BitWriter<'a, REG, RESUME>;
263impl<'a, REG> RESUME_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    ///Resume requested
268    #[inline(always)]
269    pub fn requested(self) -> &'a mut crate::W<REG> {
270        self.variant(RESUME::Requested)
271    }
272}
273/**LPM L1 Resume request
274
275Value on reset: 0*/
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum L1RESUME {
279    ///1: LPM L1 request requested
280    Requested = 1,
281}
282impl From<L1RESUME> for bool {
283    #[inline(always)]
284    fn from(variant: L1RESUME) -> Self {
285        variant as u8 != 0
286    }
287}
288///Field `L1RESUME` reader - LPM L1 Resume request
289pub type L1RESUME_R = crate::BitReader<L1RESUME>;
290impl L1RESUME_R {
291    ///Get enumerated values variant
292    #[inline(always)]
293    pub const fn variant(&self) -> Option<L1RESUME> {
294        match self.bits {
295            true => Some(L1RESUME::Requested),
296            _ => None,
297        }
298    }
299    ///LPM L1 request requested
300    #[inline(always)]
301    pub fn is_requested(&self) -> bool {
302        *self == L1RESUME::Requested
303    }
304}
305///Field `L1RESUME` writer - LPM L1 Resume request
306pub type L1RESUME_W<'a, REG> = crate::BitWriter<'a, REG, L1RESUME>;
307impl<'a, REG> L1RESUME_W<'a, REG>
308where
309    REG: crate::Writable + crate::RegisterSpec,
310{
311    ///LPM L1 request requested
312    #[inline(always)]
313    pub fn requested(self) -> &'a mut crate::W<REG> {
314        self.variant(L1RESUME::Requested)
315    }
316}
317/**LPM L1 state request interrupt mask
318
319Value on reset: 0*/
320#[cfg_attr(feature = "defmt", derive(defmt::Format))]
321#[derive(Clone, Copy, Debug, PartialEq, Eq)]
322pub enum L1REQM {
323    ///0: L1REQ Interrupt disabled
324    Disabled = 0,
325    ///1: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
326    Enabled = 1,
327}
328impl From<L1REQM> for bool {
329    #[inline(always)]
330    fn from(variant: L1REQM) -> Self {
331        variant as u8 != 0
332    }
333}
334///Field `L1REQM` reader - LPM L1 state request interrupt mask
335pub type L1REQM_R = crate::BitReader<L1REQM>;
336impl L1REQM_R {
337    ///Get enumerated values variant
338    #[inline(always)]
339    pub const fn variant(&self) -> L1REQM {
340        match self.bits {
341            false => L1REQM::Disabled,
342            true => L1REQM::Enabled,
343        }
344    }
345    ///L1REQ Interrupt disabled
346    #[inline(always)]
347    pub fn is_disabled(&self) -> bool {
348        *self == L1REQM::Disabled
349    }
350    ///L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
351    #[inline(always)]
352    pub fn is_enabled(&self) -> bool {
353        *self == L1REQM::Enabled
354    }
355}
356///Field `L1REQM` writer - LPM L1 state request interrupt mask
357pub type L1REQM_W<'a, REG> = crate::BitWriter<'a, REG, L1REQM>;
358impl<'a, REG> L1REQM_W<'a, REG>
359where
360    REG: crate::Writable + crate::RegisterSpec,
361{
362    ///L1REQ Interrupt disabled
363    #[inline(always)]
364    pub fn disabled(self) -> &'a mut crate::W<REG> {
365        self.variant(L1REQM::Disabled)
366    }
367    ///L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
368    #[inline(always)]
369    pub fn enabled(self) -> &'a mut crate::W<REG> {
370        self.variant(L1REQM::Enabled)
371    }
372}
373/**Expected start of frame interrupt mask
374
375Value on reset: 0*/
376#[cfg_attr(feature = "defmt", derive(defmt::Format))]
377#[derive(Clone, Copy, Debug, PartialEq, Eq)]
378pub enum ESOFM {
379    ///0: ESOF Interrupt disabled
380    Disabled = 0,
381    ///1: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
382    Enabled = 1,
383}
384impl From<ESOFM> for bool {
385    #[inline(always)]
386    fn from(variant: ESOFM) -> Self {
387        variant as u8 != 0
388    }
389}
390///Field `ESOFM` reader - Expected start of frame interrupt mask
391pub type ESOFM_R = crate::BitReader<ESOFM>;
392impl ESOFM_R {
393    ///Get enumerated values variant
394    #[inline(always)]
395    pub const fn variant(&self) -> ESOFM {
396        match self.bits {
397            false => ESOFM::Disabled,
398            true => ESOFM::Enabled,
399        }
400    }
401    ///ESOF Interrupt disabled
402    #[inline(always)]
403    pub fn is_disabled(&self) -> bool {
404        *self == ESOFM::Disabled
405    }
406    ///ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
407    #[inline(always)]
408    pub fn is_enabled(&self) -> bool {
409        *self == ESOFM::Enabled
410    }
411}
412///Field `ESOFM` writer - Expected start of frame interrupt mask
413pub type ESOFM_W<'a, REG> = crate::BitWriter<'a, REG, ESOFM>;
414impl<'a, REG> ESOFM_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    ///ESOF Interrupt disabled
419    #[inline(always)]
420    pub fn disabled(self) -> &'a mut crate::W<REG> {
421        self.variant(ESOFM::Disabled)
422    }
423    ///ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
424    #[inline(always)]
425    pub fn enabled(self) -> &'a mut crate::W<REG> {
426        self.variant(ESOFM::Enabled)
427    }
428}
429/**Start of frame interrupt mask
430
431Value on reset: 0*/
432#[cfg_attr(feature = "defmt", derive(defmt::Format))]
433#[derive(Clone, Copy, Debug, PartialEq, Eq)]
434pub enum SOFM {
435    ///0: SOF Interrupt disabled
436    Disabled = 0,
437    ///1: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
438    Enabled = 1,
439}
440impl From<SOFM> for bool {
441    #[inline(always)]
442    fn from(variant: SOFM) -> Self {
443        variant as u8 != 0
444    }
445}
446///Field `SOFM` reader - Start of frame interrupt mask
447pub type SOFM_R = crate::BitReader<SOFM>;
448impl SOFM_R {
449    ///Get enumerated values variant
450    #[inline(always)]
451    pub const fn variant(&self) -> SOFM {
452        match self.bits {
453            false => SOFM::Disabled,
454            true => SOFM::Enabled,
455        }
456    }
457    ///SOF Interrupt disabled
458    #[inline(always)]
459    pub fn is_disabled(&self) -> bool {
460        *self == SOFM::Disabled
461    }
462    ///SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
463    #[inline(always)]
464    pub fn is_enabled(&self) -> bool {
465        *self == SOFM::Enabled
466    }
467}
468///Field `SOFM` writer - Start of frame interrupt mask
469pub type SOFM_W<'a, REG> = crate::BitWriter<'a, REG, SOFM>;
470impl<'a, REG> SOFM_W<'a, REG>
471where
472    REG: crate::Writable + crate::RegisterSpec,
473{
474    ///SOF Interrupt disabled
475    #[inline(always)]
476    pub fn disabled(self) -> &'a mut crate::W<REG> {
477        self.variant(SOFM::Disabled)
478    }
479    ///SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
480    #[inline(always)]
481    pub fn enabled(self) -> &'a mut crate::W<REG> {
482        self.variant(SOFM::Enabled)
483    }
484}
485/**USB reset interrupt mask
486
487Value on reset: 0*/
488#[cfg_attr(feature = "defmt", derive(defmt::Format))]
489#[derive(Clone, Copy, Debug, PartialEq, Eq)]
490pub enum RESETM {
491    ///0: RESET Interrupt disabled
492    Disabled = 0,
493    ///1: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
494    Enabled = 1,
495}
496impl From<RESETM> for bool {
497    #[inline(always)]
498    fn from(variant: RESETM) -> Self {
499        variant as u8 != 0
500    }
501}
502///Field `RESETM` reader - USB reset interrupt mask
503pub type RESETM_R = crate::BitReader<RESETM>;
504impl RESETM_R {
505    ///Get enumerated values variant
506    #[inline(always)]
507    pub const fn variant(&self) -> RESETM {
508        match self.bits {
509            false => RESETM::Disabled,
510            true => RESETM::Enabled,
511        }
512    }
513    ///RESET Interrupt disabled
514    #[inline(always)]
515    pub fn is_disabled(&self) -> bool {
516        *self == RESETM::Disabled
517    }
518    ///RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
519    #[inline(always)]
520    pub fn is_enabled(&self) -> bool {
521        *self == RESETM::Enabled
522    }
523}
524///Field `RESETM` writer - USB reset interrupt mask
525pub type RESETM_W<'a, REG> = crate::BitWriter<'a, REG, RESETM>;
526impl<'a, REG> RESETM_W<'a, REG>
527where
528    REG: crate::Writable + crate::RegisterSpec,
529{
530    ///RESET Interrupt disabled
531    #[inline(always)]
532    pub fn disabled(self) -> &'a mut crate::W<REG> {
533        self.variant(RESETM::Disabled)
534    }
535    ///RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
536    #[inline(always)]
537    pub fn enabled(self) -> &'a mut crate::W<REG> {
538        self.variant(RESETM::Enabled)
539    }
540}
541/**Suspend mode interrupt mask
542
543Value on reset: 0*/
544#[cfg_attr(feature = "defmt", derive(defmt::Format))]
545#[derive(Clone, Copy, Debug, PartialEq, Eq)]
546pub enum SUSPM {
547    ///0: Suspend Mode Request SUSP Interrupt disabled
548    Disabled = 0,
549    ///1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
550    Enabled = 1,
551}
552impl From<SUSPM> for bool {
553    #[inline(always)]
554    fn from(variant: SUSPM) -> Self {
555        variant as u8 != 0
556    }
557}
558///Field `SUSPM` reader - Suspend mode interrupt mask
559pub type SUSPM_R = crate::BitReader<SUSPM>;
560impl SUSPM_R {
561    ///Get enumerated values variant
562    #[inline(always)]
563    pub const fn variant(&self) -> SUSPM {
564        match self.bits {
565            false => SUSPM::Disabled,
566            true => SUSPM::Enabled,
567        }
568    }
569    ///Suspend Mode Request SUSP Interrupt disabled
570    #[inline(always)]
571    pub fn is_disabled(&self) -> bool {
572        *self == SUSPM::Disabled
573    }
574    ///SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
575    #[inline(always)]
576    pub fn is_enabled(&self) -> bool {
577        *self == SUSPM::Enabled
578    }
579}
580///Field `SUSPM` writer - Suspend mode interrupt mask
581pub type SUSPM_W<'a, REG> = crate::BitWriter<'a, REG, SUSPM>;
582impl<'a, REG> SUSPM_W<'a, REG>
583where
584    REG: crate::Writable + crate::RegisterSpec,
585{
586    ///Suspend Mode Request SUSP Interrupt disabled
587    #[inline(always)]
588    pub fn disabled(self) -> &'a mut crate::W<REG> {
589        self.variant(SUSPM::Disabled)
590    }
591    ///SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
592    #[inline(always)]
593    pub fn enabled(self) -> &'a mut crate::W<REG> {
594        self.variant(SUSPM::Enabled)
595    }
596}
597/**Wakeup interrupt mask
598
599Value on reset: 0*/
600#[cfg_attr(feature = "defmt", derive(defmt::Format))]
601#[derive(Clone, Copy, Debug, PartialEq, Eq)]
602pub enum WKUPM {
603    ///0: WKUP Interrupt disabled
604    Disabled = 0,
605    ///1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
606    Enabled = 1,
607}
608impl From<WKUPM> for bool {
609    #[inline(always)]
610    fn from(variant: WKUPM) -> Self {
611        variant as u8 != 0
612    }
613}
614///Field `WKUPM` reader - Wakeup interrupt mask
615pub type WKUPM_R = crate::BitReader<WKUPM>;
616impl WKUPM_R {
617    ///Get enumerated values variant
618    #[inline(always)]
619    pub const fn variant(&self) -> WKUPM {
620        match self.bits {
621            false => WKUPM::Disabled,
622            true => WKUPM::Enabled,
623        }
624    }
625    ///WKUP Interrupt disabled
626    #[inline(always)]
627    pub fn is_disabled(&self) -> bool {
628        *self == WKUPM::Disabled
629    }
630    ///WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
631    #[inline(always)]
632    pub fn is_enabled(&self) -> bool {
633        *self == WKUPM::Enabled
634    }
635}
636///Field `WKUPM` writer - Wakeup interrupt mask
637pub type WKUPM_W<'a, REG> = crate::BitWriter<'a, REG, WKUPM>;
638impl<'a, REG> WKUPM_W<'a, REG>
639where
640    REG: crate::Writable + crate::RegisterSpec,
641{
642    ///WKUP Interrupt disabled
643    #[inline(always)]
644    pub fn disabled(self) -> &'a mut crate::W<REG> {
645        self.variant(WKUPM::Disabled)
646    }
647    ///WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
648    #[inline(always)]
649    pub fn enabled(self) -> &'a mut crate::W<REG> {
650        self.variant(WKUPM::Enabled)
651    }
652}
653/**Error interrupt mask
654
655Value on reset: 0*/
656#[cfg_attr(feature = "defmt", derive(defmt::Format))]
657#[derive(Clone, Copy, Debug, PartialEq, Eq)]
658pub enum ERRM {
659    ///0: ERR Interrupt disabled
660    Disabled = 0,
661    ///1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
662    Enabled = 1,
663}
664impl From<ERRM> for bool {
665    #[inline(always)]
666    fn from(variant: ERRM) -> Self {
667        variant as u8 != 0
668    }
669}
670///Field `ERRM` reader - Error interrupt mask
671pub type ERRM_R = crate::BitReader<ERRM>;
672impl ERRM_R {
673    ///Get enumerated values variant
674    #[inline(always)]
675    pub const fn variant(&self) -> ERRM {
676        match self.bits {
677            false => ERRM::Disabled,
678            true => ERRM::Enabled,
679        }
680    }
681    ///ERR Interrupt disabled
682    #[inline(always)]
683    pub fn is_disabled(&self) -> bool {
684        *self == ERRM::Disabled
685    }
686    ///ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
687    #[inline(always)]
688    pub fn is_enabled(&self) -> bool {
689        *self == ERRM::Enabled
690    }
691}
692///Field `ERRM` writer - Error interrupt mask
693pub type ERRM_W<'a, REG> = crate::BitWriter<'a, REG, ERRM>;
694impl<'a, REG> ERRM_W<'a, REG>
695where
696    REG: crate::Writable + crate::RegisterSpec,
697{
698    ///ERR Interrupt disabled
699    #[inline(always)]
700    pub fn disabled(self) -> &'a mut crate::W<REG> {
701        self.variant(ERRM::Disabled)
702    }
703    ///ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
704    #[inline(always)]
705    pub fn enabled(self) -> &'a mut crate::W<REG> {
706        self.variant(ERRM::Enabled)
707    }
708}
709/**Packet memory area over / underrun interrupt mask
710
711Value on reset: 0*/
712#[cfg_attr(feature = "defmt", derive(defmt::Format))]
713#[derive(Clone, Copy, Debug, PartialEq, Eq)]
714pub enum PMAOVRM {
715    ///0: PMAOVR Interrupt disabled
716    Disabled = 0,
717    ///1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
718    Enabled = 1,
719}
720impl From<PMAOVRM> for bool {
721    #[inline(always)]
722    fn from(variant: PMAOVRM) -> Self {
723        variant as u8 != 0
724    }
725}
726///Field `PMAOVRM` reader - Packet memory area over / underrun interrupt mask
727pub type PMAOVRM_R = crate::BitReader<PMAOVRM>;
728impl PMAOVRM_R {
729    ///Get enumerated values variant
730    #[inline(always)]
731    pub const fn variant(&self) -> PMAOVRM {
732        match self.bits {
733            false => PMAOVRM::Disabled,
734            true => PMAOVRM::Enabled,
735        }
736    }
737    ///PMAOVR Interrupt disabled
738    #[inline(always)]
739    pub fn is_disabled(&self) -> bool {
740        *self == PMAOVRM::Disabled
741    }
742    ///PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
743    #[inline(always)]
744    pub fn is_enabled(&self) -> bool {
745        *self == PMAOVRM::Enabled
746    }
747}
748///Field `PMAOVRM` writer - Packet memory area over / underrun interrupt mask
749pub type PMAOVRM_W<'a, REG> = crate::BitWriter<'a, REG, PMAOVRM>;
750impl<'a, REG> PMAOVRM_W<'a, REG>
751where
752    REG: crate::Writable + crate::RegisterSpec,
753{
754    ///PMAOVR Interrupt disabled
755    #[inline(always)]
756    pub fn disabled(self) -> &'a mut crate::W<REG> {
757        self.variant(PMAOVRM::Disabled)
758    }
759    ///PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
760    #[inline(always)]
761    pub fn enabled(self) -> &'a mut crate::W<REG> {
762        self.variant(PMAOVRM::Enabled)
763    }
764}
765/**Correct transfer interrupt mask
766
767Value on reset: 0*/
768#[cfg_attr(feature = "defmt", derive(defmt::Format))]
769#[derive(Clone, Copy, Debug, PartialEq, Eq)]
770pub enum CTRM {
771    ///0: Correct Transfer (CTR) Interrupt disabled
772    Disabled = 0,
773    ///1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
774    Enabled = 1,
775}
776impl From<CTRM> for bool {
777    #[inline(always)]
778    fn from(variant: CTRM) -> Self {
779        variant as u8 != 0
780    }
781}
782///Field `CTRM` reader - Correct transfer interrupt mask
783pub type CTRM_R = crate::BitReader<CTRM>;
784impl CTRM_R {
785    ///Get enumerated values variant
786    #[inline(always)]
787    pub const fn variant(&self) -> CTRM {
788        match self.bits {
789            false => CTRM::Disabled,
790            true => CTRM::Enabled,
791        }
792    }
793    ///Correct Transfer (CTR) Interrupt disabled
794    #[inline(always)]
795    pub fn is_disabled(&self) -> bool {
796        *self == CTRM::Disabled
797    }
798    ///CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
799    #[inline(always)]
800    pub fn is_enabled(&self) -> bool {
801        *self == CTRM::Enabled
802    }
803}
804///Field `CTRM` writer - Correct transfer interrupt mask
805pub type CTRM_W<'a, REG> = crate::BitWriter<'a, REG, CTRM>;
806impl<'a, REG> CTRM_W<'a, REG>
807where
808    REG: crate::Writable + crate::RegisterSpec,
809{
810    ///Correct Transfer (CTR) Interrupt disabled
811    #[inline(always)]
812    pub fn disabled(self) -> &'a mut crate::W<REG> {
813        self.variant(CTRM::Disabled)
814    }
815    ///CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
816    #[inline(always)]
817    pub fn enabled(self) -> &'a mut crate::W<REG> {
818        self.variant(CTRM::Enabled)
819    }
820}
821impl R {
822    ///Bit 0 - Force USB Reset
823    #[inline(always)]
824    pub fn fres(&self) -> FRES_R {
825        FRES_R::new((self.bits & 1) != 0)
826    }
827    ///Bit 1 - Power down
828    #[inline(always)]
829    pub fn pdwn(&self) -> PDWN_R {
830        PDWN_R::new(((self.bits >> 1) & 1) != 0)
831    }
832    ///Bit 2 - Low-power mode
833    #[inline(always)]
834    pub fn lpmode(&self) -> LPMODE_R {
835        LPMODE_R::new(((self.bits >> 2) & 1) != 0)
836    }
837    ///Bit 3 - Force suspend
838    #[inline(always)]
839    pub fn fsusp(&self) -> FSUSP_R {
840        FSUSP_R::new(((self.bits >> 3) & 1) != 0)
841    }
842    ///Bit 4 - Resume request
843    #[inline(always)]
844    pub fn resume(&self) -> RESUME_R {
845        RESUME_R::new(((self.bits >> 4) & 1) != 0)
846    }
847    ///Bit 5 - LPM L1 Resume request
848    #[inline(always)]
849    pub fn l1resume(&self) -> L1RESUME_R {
850        L1RESUME_R::new(((self.bits >> 5) & 1) != 0)
851    }
852    ///Bit 7 - LPM L1 state request interrupt mask
853    #[inline(always)]
854    pub fn l1reqm(&self) -> L1REQM_R {
855        L1REQM_R::new(((self.bits >> 7) & 1) != 0)
856    }
857    ///Bit 8 - Expected start of frame interrupt mask
858    #[inline(always)]
859    pub fn esofm(&self) -> ESOFM_R {
860        ESOFM_R::new(((self.bits >> 8) & 1) != 0)
861    }
862    ///Bit 9 - Start of frame interrupt mask
863    #[inline(always)]
864    pub fn sofm(&self) -> SOFM_R {
865        SOFM_R::new(((self.bits >> 9) & 1) != 0)
866    }
867    ///Bit 10 - USB reset interrupt mask
868    #[inline(always)]
869    pub fn resetm(&self) -> RESETM_R {
870        RESETM_R::new(((self.bits >> 10) & 1) != 0)
871    }
872    ///Bit 11 - Suspend mode interrupt mask
873    #[inline(always)]
874    pub fn suspm(&self) -> SUSPM_R {
875        SUSPM_R::new(((self.bits >> 11) & 1) != 0)
876    }
877    ///Bit 12 - Wakeup interrupt mask
878    #[inline(always)]
879    pub fn wkupm(&self) -> WKUPM_R {
880        WKUPM_R::new(((self.bits >> 12) & 1) != 0)
881    }
882    ///Bit 13 - Error interrupt mask
883    #[inline(always)]
884    pub fn errm(&self) -> ERRM_R {
885        ERRM_R::new(((self.bits >> 13) & 1) != 0)
886    }
887    ///Bit 14 - Packet memory area over / underrun interrupt mask
888    #[inline(always)]
889    pub fn pmaovrm(&self) -> PMAOVRM_R {
890        PMAOVRM_R::new(((self.bits >> 14) & 1) != 0)
891    }
892    ///Bit 15 - Correct transfer interrupt mask
893    #[inline(always)]
894    pub fn ctrm(&self) -> CTRM_R {
895        CTRM_R::new(((self.bits >> 15) & 1) != 0)
896    }
897}
898impl core::fmt::Debug for R {
899    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
900        f.debug_struct("CNTR")
901            .field("fres", &self.fres())
902            .field("pdwn", &self.pdwn())
903            .field("lpmode", &self.lpmode())
904            .field("fsusp", &self.fsusp())
905            .field("resume", &self.resume())
906            .field("l1resume", &self.l1resume())
907            .field("l1reqm", &self.l1reqm())
908            .field("esofm", &self.esofm())
909            .field("sofm", &self.sofm())
910            .field("resetm", &self.resetm())
911            .field("suspm", &self.suspm())
912            .field("wkupm", &self.wkupm())
913            .field("errm", &self.errm())
914            .field("pmaovrm", &self.pmaovrm())
915            .field("ctrm", &self.ctrm())
916            .finish()
917    }
918}
919impl W {
920    ///Bit 0 - Force USB Reset
921    #[inline(always)]
922    pub fn fres(&mut self) -> FRES_W<CNTRrs> {
923        FRES_W::new(self, 0)
924    }
925    ///Bit 1 - Power down
926    #[inline(always)]
927    pub fn pdwn(&mut self) -> PDWN_W<CNTRrs> {
928        PDWN_W::new(self, 1)
929    }
930    ///Bit 2 - Low-power mode
931    #[inline(always)]
932    pub fn lpmode(&mut self) -> LPMODE_W<CNTRrs> {
933        LPMODE_W::new(self, 2)
934    }
935    ///Bit 3 - Force suspend
936    #[inline(always)]
937    pub fn fsusp(&mut self) -> FSUSP_W<CNTRrs> {
938        FSUSP_W::new(self, 3)
939    }
940    ///Bit 4 - Resume request
941    #[inline(always)]
942    pub fn resume(&mut self) -> RESUME_W<CNTRrs> {
943        RESUME_W::new(self, 4)
944    }
945    ///Bit 5 - LPM L1 Resume request
946    #[inline(always)]
947    pub fn l1resume(&mut self) -> L1RESUME_W<CNTRrs> {
948        L1RESUME_W::new(self, 5)
949    }
950    ///Bit 7 - LPM L1 state request interrupt mask
951    #[inline(always)]
952    pub fn l1reqm(&mut self) -> L1REQM_W<CNTRrs> {
953        L1REQM_W::new(self, 7)
954    }
955    ///Bit 8 - Expected start of frame interrupt mask
956    #[inline(always)]
957    pub fn esofm(&mut self) -> ESOFM_W<CNTRrs> {
958        ESOFM_W::new(self, 8)
959    }
960    ///Bit 9 - Start of frame interrupt mask
961    #[inline(always)]
962    pub fn sofm(&mut self) -> SOFM_W<CNTRrs> {
963        SOFM_W::new(self, 9)
964    }
965    ///Bit 10 - USB reset interrupt mask
966    #[inline(always)]
967    pub fn resetm(&mut self) -> RESETM_W<CNTRrs> {
968        RESETM_W::new(self, 10)
969    }
970    ///Bit 11 - Suspend mode interrupt mask
971    #[inline(always)]
972    pub fn suspm(&mut self) -> SUSPM_W<CNTRrs> {
973        SUSPM_W::new(self, 11)
974    }
975    ///Bit 12 - Wakeup interrupt mask
976    #[inline(always)]
977    pub fn wkupm(&mut self) -> WKUPM_W<CNTRrs> {
978        WKUPM_W::new(self, 12)
979    }
980    ///Bit 13 - Error interrupt mask
981    #[inline(always)]
982    pub fn errm(&mut self) -> ERRM_W<CNTRrs> {
983        ERRM_W::new(self, 13)
984    }
985    ///Bit 14 - Packet memory area over / underrun interrupt mask
986    #[inline(always)]
987    pub fn pmaovrm(&mut self) -> PMAOVRM_W<CNTRrs> {
988        PMAOVRM_W::new(self, 14)
989    }
990    ///Bit 15 - Correct transfer interrupt mask
991    #[inline(always)]
992    pub fn ctrm(&mut self) -> CTRM_W<CNTRrs> {
993        CTRM_W::new(self, 15)
994    }
995}
996/**control register
997
998You can [`read`](crate::Reg::read) this register and get [`cntr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cntr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
999
1000See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x1.html#USB:CNTR)*/
1001pub struct CNTRrs;
1002impl crate::RegisterSpec for CNTRrs {
1003    type Ux = u32;
1004}
1005///`read()` method returns [`cntr::R`](R) reader structure
1006impl crate::Readable for CNTRrs {}
1007///`write(|w| ..)` method takes [`cntr::W`](W) writer structure
1008impl crate::Writable for CNTRrs {
1009    type Safety = crate::Unsafe;
1010}
1011///`reset()` method sets CNTR to value 0x03
1012impl crate::Resettable for CNTRrs {
1013    const RESET_VALUE: u32 = 0x03;
1014}
stm32f0/stm32f0x1/usb/cntr.rs

stm32f0/stm32f0x1/usb/
cntr.rs
