stm32f0/stm32f0x0/adc/
cfgr1.rs

1///Register `CFGR1` reader
2pub type R = crate::R<CFGR1rs>;
3///Register `CFGR1` writer
4pub type W = crate::W<CFGR1rs>;
5/**Direct memory access enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DMAEN {
11    ///0: DMA mode disabled
12    Disabled = 0,
13    ///1: DMA mode enabled
14    Enabled = 1,
15}
16impl From<DMAEN> for bool {
17    #[inline(always)]
18    fn from(variant: DMAEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DMAEN` reader - Direct memory access enable
23pub type DMAEN_R = crate::BitReader<DMAEN>;
24impl DMAEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DMAEN {
28        match self.bits {
29            false => DMAEN::Disabled,
30            true => DMAEN::Enabled,
31        }
32    }
33    ///DMA mode disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == DMAEN::Disabled
37    }
38    ///DMA mode enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == DMAEN::Enabled
42    }
43}
44///Field `DMAEN` writer - Direct memory access enable
45pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN>;
46impl<'a, REG> DMAEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///DMA mode disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(DMAEN::Disabled)
54    }
55    ///DMA mode enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(DMAEN::Enabled)
59    }
60}
61/**Direct memery access configuration
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum DMACFG {
67    ///0: DMA one shot mode
68    OneShot = 0,
69    ///1: DMA circular mode
70    Circular = 1,
71}
72impl From<DMACFG> for bool {
73    #[inline(always)]
74    fn from(variant: DMACFG) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `DMACFG` reader - Direct memery access configuration
79pub type DMACFG_R = crate::BitReader<DMACFG>;
80impl DMACFG_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> DMACFG {
84        match self.bits {
85            false => DMACFG::OneShot,
86            true => DMACFG::Circular,
87        }
88    }
89    ///DMA one shot mode
90    #[inline(always)]
91    pub fn is_one_shot(&self) -> bool {
92        *self == DMACFG::OneShot
93    }
94    ///DMA circular mode
95    #[inline(always)]
96    pub fn is_circular(&self) -> bool {
97        *self == DMACFG::Circular
98    }
99}
100///Field `DMACFG` writer - Direct memery access configuration
101pub type DMACFG_W<'a, REG> = crate::BitWriter<'a, REG, DMACFG>;
102impl<'a, REG> DMACFG_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///DMA one shot mode
107    #[inline(always)]
108    pub fn one_shot(self) -> &'a mut crate::W<REG> {
109        self.variant(DMACFG::OneShot)
110    }
111    ///DMA circular mode
112    #[inline(always)]
113    pub fn circular(self) -> &'a mut crate::W<REG> {
114        self.variant(DMACFG::Circular)
115    }
116}
117/**Scan sequence direction
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum SCANDIR {
123    ///0: Upward scan (from CHSEL0 to CHSEL18)
124    Upward = 0,
125    ///1: Backward scan (from CHSEL18 to CHSEL0)
126    Backward = 1,
127}
128impl From<SCANDIR> for bool {
129    #[inline(always)]
130    fn from(variant: SCANDIR) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `SCANDIR` reader - Scan sequence direction
135pub type SCANDIR_R = crate::BitReader<SCANDIR>;
136impl SCANDIR_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> SCANDIR {
140        match self.bits {
141            false => SCANDIR::Upward,
142            true => SCANDIR::Backward,
143        }
144    }
145    ///Upward scan (from CHSEL0 to CHSEL18)
146    #[inline(always)]
147    pub fn is_upward(&self) -> bool {
148        *self == SCANDIR::Upward
149    }
150    ///Backward scan (from CHSEL18 to CHSEL0)
151    #[inline(always)]
152    pub fn is_backward(&self) -> bool {
153        *self == SCANDIR::Backward
154    }
155}
156///Field `SCANDIR` writer - Scan sequence direction
157pub type SCANDIR_W<'a, REG> = crate::BitWriter<'a, REG, SCANDIR>;
158impl<'a, REG> SCANDIR_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Upward scan (from CHSEL0 to CHSEL18)
163    #[inline(always)]
164    pub fn upward(self) -> &'a mut crate::W<REG> {
165        self.variant(SCANDIR::Upward)
166    }
167    ///Backward scan (from CHSEL18 to CHSEL0)
168    #[inline(always)]
169    pub fn backward(self) -> &'a mut crate::W<REG> {
170        self.variant(SCANDIR::Backward)
171    }
172}
173/**Data resolution
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178#[repr(u8)]
179pub enum RES {
180    ///0: 12-bit (14 ADCCLK cycles)
181    TwelveBit = 0,
182    ///1: 10-bit (13 ADCCLK cycles)
183    TenBit = 1,
184    ///2: 8-bit (11 ADCCLK cycles)
185    EightBit = 2,
186    ///3: 6-bit (9 ADCCLK cycles)
187    SixBit = 3,
188}
189impl From<RES> for u8 {
190    #[inline(always)]
191    fn from(variant: RES) -> Self {
192        variant as _
193    }
194}
195impl crate::FieldSpec for RES {
196    type Ux = u8;
197}
198impl crate::IsEnum for RES {}
199///Field `RES` reader - Data resolution
200pub type RES_R = crate::FieldReader<RES>;
201impl RES_R {
202    ///Get enumerated values variant
203    #[inline(always)]
204    pub const fn variant(&self) -> RES {
205        match self.bits {
206            0 => RES::TwelveBit,
207            1 => RES::TenBit,
208            2 => RES::EightBit,
209            3 => RES::SixBit,
210            _ => unreachable!(),
211        }
212    }
213    ///12-bit (14 ADCCLK cycles)
214    #[inline(always)]
215    pub fn is_twelve_bit(&self) -> bool {
216        *self == RES::TwelveBit
217    }
218    ///10-bit (13 ADCCLK cycles)
219    #[inline(always)]
220    pub fn is_ten_bit(&self) -> bool {
221        *self == RES::TenBit
222    }
223    ///8-bit (11 ADCCLK cycles)
224    #[inline(always)]
225    pub fn is_eight_bit(&self) -> bool {
226        *self == RES::EightBit
227    }
228    ///6-bit (9 ADCCLK cycles)
229    #[inline(always)]
230    pub fn is_six_bit(&self) -> bool {
231        *self == RES::SixBit
232    }
233}
234///Field `RES` writer - Data resolution
235pub type RES_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RES, crate::Safe>;
236impl<'a, REG> RES_W<'a, REG>
237where
238    REG: crate::Writable + crate::RegisterSpec,
239    REG::Ux: From<u8>,
240{
241    ///12-bit (14 ADCCLK cycles)
242    #[inline(always)]
243    pub fn twelve_bit(self) -> &'a mut crate::W<REG> {
244        self.variant(RES::TwelveBit)
245    }
246    ///10-bit (13 ADCCLK cycles)
247    #[inline(always)]
248    pub fn ten_bit(self) -> &'a mut crate::W<REG> {
249        self.variant(RES::TenBit)
250    }
251    ///8-bit (11 ADCCLK cycles)
252    #[inline(always)]
253    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
254        self.variant(RES::EightBit)
255    }
256    ///6-bit (9 ADCCLK cycles)
257    #[inline(always)]
258    pub fn six_bit(self) -> &'a mut crate::W<REG> {
259        self.variant(RES::SixBit)
260    }
261}
262/**Data alignment
263
264Value on reset: 0*/
265#[cfg_attr(feature = "defmt", derive(defmt::Format))]
266#[derive(Clone, Copy, Debug, PartialEq, Eq)]
267pub enum ALIGN {
268    ///0: Right alignment
269    Right = 0,
270    ///1: Left alignment
271    Left = 1,
272}
273impl From<ALIGN> for bool {
274    #[inline(always)]
275    fn from(variant: ALIGN) -> Self {
276        variant as u8 != 0
277    }
278}
279///Field `ALIGN` reader - Data alignment
280pub type ALIGN_R = crate::BitReader<ALIGN>;
281impl ALIGN_R {
282    ///Get enumerated values variant
283    #[inline(always)]
284    pub const fn variant(&self) -> ALIGN {
285        match self.bits {
286            false => ALIGN::Right,
287            true => ALIGN::Left,
288        }
289    }
290    ///Right alignment
291    #[inline(always)]
292    pub fn is_right(&self) -> bool {
293        *self == ALIGN::Right
294    }
295    ///Left alignment
296    #[inline(always)]
297    pub fn is_left(&self) -> bool {
298        *self == ALIGN::Left
299    }
300}
301///Field `ALIGN` writer - Data alignment
302pub type ALIGN_W<'a, REG> = crate::BitWriter<'a, REG, ALIGN>;
303impl<'a, REG> ALIGN_W<'a, REG>
304where
305    REG: crate::Writable + crate::RegisterSpec,
306{
307    ///Right alignment
308    #[inline(always)]
309    pub fn right(self) -> &'a mut crate::W<REG> {
310        self.variant(ALIGN::Right)
311    }
312    ///Left alignment
313    #[inline(always)]
314    pub fn left(self) -> &'a mut crate::W<REG> {
315        self.variant(ALIGN::Left)
316    }
317}
318/**External trigger selection
319
320Value on reset: 0*/
321#[cfg_attr(feature = "defmt", derive(defmt::Format))]
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323#[repr(u8)]
324pub enum EXTSEL {
325    ///0: Timer 1 TRGO Event
326    Tim1Trgo = 0,
327    ///1: Timer 1 CC4 event
328    Tim1Cc4 = 1,
329    ///3: Timer 3 TRGO event
330    Tim3Trgo = 3,
331    ///4: Timer 15 TRGO event
332    Tim15Trgo = 4,
333}
334impl From<EXTSEL> for u8 {
335    #[inline(always)]
336    fn from(variant: EXTSEL) -> Self {
337        variant as _
338    }
339}
340impl crate::FieldSpec for EXTSEL {
341    type Ux = u8;
342}
343impl crate::IsEnum for EXTSEL {}
344///Field `EXTSEL` reader - External trigger selection
345pub type EXTSEL_R = crate::FieldReader<EXTSEL>;
346impl EXTSEL_R {
347    ///Get enumerated values variant
348    #[inline(always)]
349    pub const fn variant(&self) -> Option<EXTSEL> {
350        match self.bits {
351            0 => Some(EXTSEL::Tim1Trgo),
352            1 => Some(EXTSEL::Tim1Cc4),
353            3 => Some(EXTSEL::Tim3Trgo),
354            4 => Some(EXTSEL::Tim15Trgo),
355            _ => None,
356        }
357    }
358    ///Timer 1 TRGO Event
359    #[inline(always)]
360    pub fn is_tim1_trgo(&self) -> bool {
361        *self == EXTSEL::Tim1Trgo
362    }
363    ///Timer 1 CC4 event
364    #[inline(always)]
365    pub fn is_tim1_cc4(&self) -> bool {
366        *self == EXTSEL::Tim1Cc4
367    }
368    ///Timer 3 TRGO event
369    #[inline(always)]
370    pub fn is_tim3_trgo(&self) -> bool {
371        *self == EXTSEL::Tim3Trgo
372    }
373    ///Timer 15 TRGO event
374    #[inline(always)]
375    pub fn is_tim15_trgo(&self) -> bool {
376        *self == EXTSEL::Tim15Trgo
377    }
378}
379///Field `EXTSEL` writer - External trigger selection
380pub type EXTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, EXTSEL>;
381impl<'a, REG> EXTSEL_W<'a, REG>
382where
383    REG: crate::Writable + crate::RegisterSpec,
384    REG::Ux: From<u8>,
385{
386    ///Timer 1 TRGO Event
387    #[inline(always)]
388    pub fn tim1_trgo(self) -> &'a mut crate::W<REG> {
389        self.variant(EXTSEL::Tim1Trgo)
390    }
391    ///Timer 1 CC4 event
392    #[inline(always)]
393    pub fn tim1_cc4(self) -> &'a mut crate::W<REG> {
394        self.variant(EXTSEL::Tim1Cc4)
395    }
396    ///Timer 3 TRGO event
397    #[inline(always)]
398    pub fn tim3_trgo(self) -> &'a mut crate::W<REG> {
399        self.variant(EXTSEL::Tim3Trgo)
400    }
401    ///Timer 15 TRGO event
402    #[inline(always)]
403    pub fn tim15_trgo(self) -> &'a mut crate::W<REG> {
404        self.variant(EXTSEL::Tim15Trgo)
405    }
406}
407/**External trigger enable and polarity selection
408
409Value on reset: 0*/
410#[cfg_attr(feature = "defmt", derive(defmt::Format))]
411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
412#[repr(u8)]
413pub enum EXTEN {
414    ///0: Trigger detection disabled
415    Disabled = 0,
416    ///1: Trigger detection on the rising edge
417    RisingEdge = 1,
418    ///2: Trigger detection on the falling edge
419    FallingEdge = 2,
420    ///3: Trigger detection on both the rising and falling edges
421    BothEdges = 3,
422}
423impl From<EXTEN> for u8 {
424    #[inline(always)]
425    fn from(variant: EXTEN) -> Self {
426        variant as _
427    }
428}
429impl crate::FieldSpec for EXTEN {
430    type Ux = u8;
431}
432impl crate::IsEnum for EXTEN {}
433///Field `EXTEN` reader - External trigger enable and polarity selection
434pub type EXTEN_R = crate::FieldReader<EXTEN>;
435impl EXTEN_R {
436    ///Get enumerated values variant
437    #[inline(always)]
438    pub const fn variant(&self) -> EXTEN {
439        match self.bits {
440            0 => EXTEN::Disabled,
441            1 => EXTEN::RisingEdge,
442            2 => EXTEN::FallingEdge,
443            3 => EXTEN::BothEdges,
444            _ => unreachable!(),
445        }
446    }
447    ///Trigger detection disabled
448    #[inline(always)]
449    pub fn is_disabled(&self) -> bool {
450        *self == EXTEN::Disabled
451    }
452    ///Trigger detection on the rising edge
453    #[inline(always)]
454    pub fn is_rising_edge(&self) -> bool {
455        *self == EXTEN::RisingEdge
456    }
457    ///Trigger detection on the falling edge
458    #[inline(always)]
459    pub fn is_falling_edge(&self) -> bool {
460        *self == EXTEN::FallingEdge
461    }
462    ///Trigger detection on both the rising and falling edges
463    #[inline(always)]
464    pub fn is_both_edges(&self) -> bool {
465        *self == EXTEN::BothEdges
466    }
467}
468///Field `EXTEN` writer - External trigger enable and polarity selection
469pub type EXTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EXTEN, crate::Safe>;
470impl<'a, REG> EXTEN_W<'a, REG>
471where
472    REG: crate::Writable + crate::RegisterSpec,
473    REG::Ux: From<u8>,
474{
475    ///Trigger detection disabled
476    #[inline(always)]
477    pub fn disabled(self) -> &'a mut crate::W<REG> {
478        self.variant(EXTEN::Disabled)
479    }
480    ///Trigger detection on the rising edge
481    #[inline(always)]
482    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
483        self.variant(EXTEN::RisingEdge)
484    }
485    ///Trigger detection on the falling edge
486    #[inline(always)]
487    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
488        self.variant(EXTEN::FallingEdge)
489    }
490    ///Trigger detection on both the rising and falling edges
491    #[inline(always)]
492    pub fn both_edges(self) -> &'a mut crate::W<REG> {
493        self.variant(EXTEN::BothEdges)
494    }
495}
496/**Overrun management mode
497
498Value on reset: 0*/
499#[cfg_attr(feature = "defmt", derive(defmt::Format))]
500#[derive(Clone, Copy, Debug, PartialEq, Eq)]
501pub enum OVRMOD {
502    ///0: ADC_DR register is preserved with the old data when an overrun is detected
503    Preserved = 0,
504    ///1: ADC_DR register is overwritten with the last conversion result when an overrun is detected
505    Overwritten = 1,
506}
507impl From<OVRMOD> for bool {
508    #[inline(always)]
509    fn from(variant: OVRMOD) -> Self {
510        variant as u8 != 0
511    }
512}
513///Field `OVRMOD` reader - Overrun management mode
514pub type OVRMOD_R = crate::BitReader<OVRMOD>;
515impl OVRMOD_R {
516    ///Get enumerated values variant
517    #[inline(always)]
518    pub const fn variant(&self) -> OVRMOD {
519        match self.bits {
520            false => OVRMOD::Preserved,
521            true => OVRMOD::Overwritten,
522        }
523    }
524    ///ADC_DR register is preserved with the old data when an overrun is detected
525    #[inline(always)]
526    pub fn is_preserved(&self) -> bool {
527        *self == OVRMOD::Preserved
528    }
529    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
530    #[inline(always)]
531    pub fn is_overwritten(&self) -> bool {
532        *self == OVRMOD::Overwritten
533    }
534}
535///Field `OVRMOD` writer - Overrun management mode
536pub type OVRMOD_W<'a, REG> = crate::BitWriter<'a, REG, OVRMOD>;
537impl<'a, REG> OVRMOD_W<'a, REG>
538where
539    REG: crate::Writable + crate::RegisterSpec,
540{
541    ///ADC_DR register is preserved with the old data when an overrun is detected
542    #[inline(always)]
543    pub fn preserved(self) -> &'a mut crate::W<REG> {
544        self.variant(OVRMOD::Preserved)
545    }
546    ///ADC_DR register is overwritten with the last conversion result when an overrun is detected
547    #[inline(always)]
548    pub fn overwritten(self) -> &'a mut crate::W<REG> {
549        self.variant(OVRMOD::Overwritten)
550    }
551}
552/**Single / continuous conversion mode
553
554Value on reset: 0*/
555#[cfg_attr(feature = "defmt", derive(defmt::Format))]
556#[derive(Clone, Copy, Debug, PartialEq, Eq)]
557pub enum CONT {
558    ///0: Single conversion mode
559    Single = 0,
560    ///1: Continuous conversion mode
561    Continuous = 1,
562}
563impl From<CONT> for bool {
564    #[inline(always)]
565    fn from(variant: CONT) -> Self {
566        variant as u8 != 0
567    }
568}
569///Field `CONT` reader - Single / continuous conversion mode
570pub type CONT_R = crate::BitReader<CONT>;
571impl CONT_R {
572    ///Get enumerated values variant
573    #[inline(always)]
574    pub const fn variant(&self) -> CONT {
575        match self.bits {
576            false => CONT::Single,
577            true => CONT::Continuous,
578        }
579    }
580    ///Single conversion mode
581    #[inline(always)]
582    pub fn is_single(&self) -> bool {
583        *self == CONT::Single
584    }
585    ///Continuous conversion mode
586    #[inline(always)]
587    pub fn is_continuous(&self) -> bool {
588        *self == CONT::Continuous
589    }
590}
591///Field `CONT` writer - Single / continuous conversion mode
592pub type CONT_W<'a, REG> = crate::BitWriter<'a, REG, CONT>;
593impl<'a, REG> CONT_W<'a, REG>
594where
595    REG: crate::Writable + crate::RegisterSpec,
596{
597    ///Single conversion mode
598    #[inline(always)]
599    pub fn single(self) -> &'a mut crate::W<REG> {
600        self.variant(CONT::Single)
601    }
602    ///Continuous conversion mode
603    #[inline(always)]
604    pub fn continuous(self) -> &'a mut crate::W<REG> {
605        self.variant(CONT::Continuous)
606    }
607}
608/**Wait conversion mode
609
610Value on reset: 0*/
611#[cfg_attr(feature = "defmt", derive(defmt::Format))]
612#[derive(Clone, Copy, Debug, PartialEq, Eq)]
613pub enum WAIT {
614    ///0: Wait conversion mode off
615    Disabled = 0,
616    ///1: Wait conversion mode on
617    Enabled = 1,
618}
619impl From<WAIT> for bool {
620    #[inline(always)]
621    fn from(variant: WAIT) -> Self {
622        variant as u8 != 0
623    }
624}
625///Field `WAIT` reader - Wait conversion mode
626pub type WAIT_R = crate::BitReader<WAIT>;
627impl WAIT_R {
628    ///Get enumerated values variant
629    #[inline(always)]
630    pub const fn variant(&self) -> WAIT {
631        match self.bits {
632            false => WAIT::Disabled,
633            true => WAIT::Enabled,
634        }
635    }
636    ///Wait conversion mode off
637    #[inline(always)]
638    pub fn is_disabled(&self) -> bool {
639        *self == WAIT::Disabled
640    }
641    ///Wait conversion mode on
642    #[inline(always)]
643    pub fn is_enabled(&self) -> bool {
644        *self == WAIT::Enabled
645    }
646}
647///Field `WAIT` writer - Wait conversion mode
648pub type WAIT_W<'a, REG> = crate::BitWriter<'a, REG, WAIT>;
649impl<'a, REG> WAIT_W<'a, REG>
650where
651    REG: crate::Writable + crate::RegisterSpec,
652{
653    ///Wait conversion mode off
654    #[inline(always)]
655    pub fn disabled(self) -> &'a mut crate::W<REG> {
656        self.variant(WAIT::Disabled)
657    }
658    ///Wait conversion mode on
659    #[inline(always)]
660    pub fn enabled(self) -> &'a mut crate::W<REG> {
661        self.variant(WAIT::Enabled)
662    }
663}
664/**Auto-off mode
665
666Value on reset: 0*/
667#[cfg_attr(feature = "defmt", derive(defmt::Format))]
668#[derive(Clone, Copy, Debug, PartialEq, Eq)]
669pub enum AUTOFF {
670    ///0: Auto-off mode disabled
671    Disabled = 0,
672    ///1: Auto-off mode enabled
673    Enabled = 1,
674}
675impl From<AUTOFF> for bool {
676    #[inline(always)]
677    fn from(variant: AUTOFF) -> Self {
678        variant as u8 != 0
679    }
680}
681///Field `AUTOFF` reader - Auto-off mode
682pub type AUTOFF_R = crate::BitReader<AUTOFF>;
683impl AUTOFF_R {
684    ///Get enumerated values variant
685    #[inline(always)]
686    pub const fn variant(&self) -> AUTOFF {
687        match self.bits {
688            false => AUTOFF::Disabled,
689            true => AUTOFF::Enabled,
690        }
691    }
692    ///Auto-off mode disabled
693    #[inline(always)]
694    pub fn is_disabled(&self) -> bool {
695        *self == AUTOFF::Disabled
696    }
697    ///Auto-off mode enabled
698    #[inline(always)]
699    pub fn is_enabled(&self) -> bool {
700        *self == AUTOFF::Enabled
701    }
702}
703///Field `AUTOFF` writer - Auto-off mode
704pub type AUTOFF_W<'a, REG> = crate::BitWriter<'a, REG, AUTOFF>;
705impl<'a, REG> AUTOFF_W<'a, REG>
706where
707    REG: crate::Writable + crate::RegisterSpec,
708{
709    ///Auto-off mode disabled
710    #[inline(always)]
711    pub fn disabled(self) -> &'a mut crate::W<REG> {
712        self.variant(AUTOFF::Disabled)
713    }
714    ///Auto-off mode enabled
715    #[inline(always)]
716    pub fn enabled(self) -> &'a mut crate::W<REG> {
717        self.variant(AUTOFF::Enabled)
718    }
719}
720/**Discontinuous mode
721
722Value on reset: 0*/
723#[cfg_attr(feature = "defmt", derive(defmt::Format))]
724#[derive(Clone, Copy, Debug, PartialEq, Eq)]
725pub enum DISCEN {
726    ///0: Discontinuous mode on regular channels disabled
727    Disabled = 0,
728    ///1: Discontinuous mode on regular channels enabled
729    Enabled = 1,
730}
731impl From<DISCEN> for bool {
732    #[inline(always)]
733    fn from(variant: DISCEN) -> Self {
734        variant as u8 != 0
735    }
736}
737///Field `DISCEN` reader - Discontinuous mode
738pub type DISCEN_R = crate::BitReader<DISCEN>;
739impl DISCEN_R {
740    ///Get enumerated values variant
741    #[inline(always)]
742    pub const fn variant(&self) -> DISCEN {
743        match self.bits {
744            false => DISCEN::Disabled,
745            true => DISCEN::Enabled,
746        }
747    }
748    ///Discontinuous mode on regular channels disabled
749    #[inline(always)]
750    pub fn is_disabled(&self) -> bool {
751        *self == DISCEN::Disabled
752    }
753    ///Discontinuous mode on regular channels enabled
754    #[inline(always)]
755    pub fn is_enabled(&self) -> bool {
756        *self == DISCEN::Enabled
757    }
758}
759///Field `DISCEN` writer - Discontinuous mode
760pub type DISCEN_W<'a, REG> = crate::BitWriter<'a, REG, DISCEN>;
761impl<'a, REG> DISCEN_W<'a, REG>
762where
763    REG: crate::Writable + crate::RegisterSpec,
764{
765    ///Discontinuous mode on regular channels disabled
766    #[inline(always)]
767    pub fn disabled(self) -> &'a mut crate::W<REG> {
768        self.variant(DISCEN::Disabled)
769    }
770    ///Discontinuous mode on regular channels enabled
771    #[inline(always)]
772    pub fn enabled(self) -> &'a mut crate::W<REG> {
773        self.variant(DISCEN::Enabled)
774    }
775}
776/**Enable the watchdog on a single channel or on all channels
777
778Value on reset: 0*/
779#[cfg_attr(feature = "defmt", derive(defmt::Format))]
780#[derive(Clone, Copy, Debug, PartialEq, Eq)]
781pub enum AWDSGL {
782    ///0: Analog watchdog enabled on all channels
783    AllChannels = 0,
784    ///1: Analog watchdog enabled on a single channel
785    SingleChannel = 1,
786}
787impl From<AWDSGL> for bool {
788    #[inline(always)]
789    fn from(variant: AWDSGL) -> Self {
790        variant as u8 != 0
791    }
792}
793///Field `AWDSGL` reader - Enable the watchdog on a single channel or on all channels
794pub type AWDSGL_R = crate::BitReader<AWDSGL>;
795impl AWDSGL_R {
796    ///Get enumerated values variant
797    #[inline(always)]
798    pub const fn variant(&self) -> AWDSGL {
799        match self.bits {
800            false => AWDSGL::AllChannels,
801            true => AWDSGL::SingleChannel,
802        }
803    }
804    ///Analog watchdog enabled on all channels
805    #[inline(always)]
806    pub fn is_all_channels(&self) -> bool {
807        *self == AWDSGL::AllChannels
808    }
809    ///Analog watchdog enabled on a single channel
810    #[inline(always)]
811    pub fn is_single_channel(&self) -> bool {
812        *self == AWDSGL::SingleChannel
813    }
814}
815///Field `AWDSGL` writer - Enable the watchdog on a single channel or on all channels
816pub type AWDSGL_W<'a, REG> = crate::BitWriter<'a, REG, AWDSGL>;
817impl<'a, REG> AWDSGL_W<'a, REG>
818where
819    REG: crate::Writable + crate::RegisterSpec,
820{
821    ///Analog watchdog enabled on all channels
822    #[inline(always)]
823    pub fn all_channels(self) -> &'a mut crate::W<REG> {
824        self.variant(AWDSGL::AllChannels)
825    }
826    ///Analog watchdog enabled on a single channel
827    #[inline(always)]
828    pub fn single_channel(self) -> &'a mut crate::W<REG> {
829        self.variant(AWDSGL::SingleChannel)
830    }
831}
832/**Analog watchdog enable
833
834Value on reset: 0*/
835#[cfg_attr(feature = "defmt", derive(defmt::Format))]
836#[derive(Clone, Copy, Debug, PartialEq, Eq)]
837pub enum AWDEN {
838    ///0: Analog watchdog disabled on regular channels
839    Disabled = 0,
840    ///1: Analog watchdog enabled on regular channels
841    Enabled = 1,
842}
843impl From<AWDEN> for bool {
844    #[inline(always)]
845    fn from(variant: AWDEN) -> Self {
846        variant as u8 != 0
847    }
848}
849///Field `AWDEN` reader - Analog watchdog enable
850pub type AWDEN_R = crate::BitReader<AWDEN>;
851impl AWDEN_R {
852    ///Get enumerated values variant
853    #[inline(always)]
854    pub const fn variant(&self) -> AWDEN {
855        match self.bits {
856            false => AWDEN::Disabled,
857            true => AWDEN::Enabled,
858        }
859    }
860    ///Analog watchdog disabled on regular channels
861    #[inline(always)]
862    pub fn is_disabled(&self) -> bool {
863        *self == AWDEN::Disabled
864    }
865    ///Analog watchdog enabled on regular channels
866    #[inline(always)]
867    pub fn is_enabled(&self) -> bool {
868        *self == AWDEN::Enabled
869    }
870}
871///Field `AWDEN` writer - Analog watchdog enable
872pub type AWDEN_W<'a, REG> = crate::BitWriter<'a, REG, AWDEN>;
873impl<'a, REG> AWDEN_W<'a, REG>
874where
875    REG: crate::Writable + crate::RegisterSpec,
876{
877    ///Analog watchdog disabled on regular channels
878    #[inline(always)]
879    pub fn disabled(self) -> &'a mut crate::W<REG> {
880        self.variant(AWDEN::Disabled)
881    }
882    ///Analog watchdog enabled on regular channels
883    #[inline(always)]
884    pub fn enabled(self) -> &'a mut crate::W<REG> {
885        self.variant(AWDEN::Enabled)
886    }
887}
888///Field `AWDCH` reader - Analog watchdog channel selection
889pub type AWDCH_R = crate::FieldReader;
890///Field `AWDCH` writer - Analog watchdog channel selection
891pub type AWDCH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
892impl R {
893    ///Bit 0 - Direct memory access enable
894    #[inline(always)]
895    pub fn dmaen(&self) -> DMAEN_R {
896        DMAEN_R::new((self.bits & 1) != 0)
897    }
898    ///Bit 1 - Direct memery access configuration
899    #[inline(always)]
900    pub fn dmacfg(&self) -> DMACFG_R {
901        DMACFG_R::new(((self.bits >> 1) & 1) != 0)
902    }
903    ///Bit 2 - Scan sequence direction
904    #[inline(always)]
905    pub fn scandir(&self) -> SCANDIR_R {
906        SCANDIR_R::new(((self.bits >> 2) & 1) != 0)
907    }
908    ///Bits 3:4 - Data resolution
909    #[inline(always)]
910    pub fn res(&self) -> RES_R {
911        RES_R::new(((self.bits >> 3) & 3) as u8)
912    }
913    ///Bit 5 - Data alignment
914    #[inline(always)]
915    pub fn align(&self) -> ALIGN_R {
916        ALIGN_R::new(((self.bits >> 5) & 1) != 0)
917    }
918    ///Bits 6:8 - External trigger selection
919    #[inline(always)]
920    pub fn extsel(&self) -> EXTSEL_R {
921        EXTSEL_R::new(((self.bits >> 6) & 7) as u8)
922    }
923    ///Bits 10:11 - External trigger enable and polarity selection
924    #[inline(always)]
925    pub fn exten(&self) -> EXTEN_R {
926        EXTEN_R::new(((self.bits >> 10) & 3) as u8)
927    }
928    ///Bit 12 - Overrun management mode
929    #[inline(always)]
930    pub fn ovrmod(&self) -> OVRMOD_R {
931        OVRMOD_R::new(((self.bits >> 12) & 1) != 0)
932    }
933    ///Bit 13 - Single / continuous conversion mode
934    #[inline(always)]
935    pub fn cont(&self) -> CONT_R {
936        CONT_R::new(((self.bits >> 13) & 1) != 0)
937    }
938    ///Bit 14 - Wait conversion mode
939    #[inline(always)]
940    pub fn wait(&self) -> WAIT_R {
941        WAIT_R::new(((self.bits >> 14) & 1) != 0)
942    }
943    ///Bit 15 - Auto-off mode
944    #[inline(always)]
945    pub fn autoff(&self) -> AUTOFF_R {
946        AUTOFF_R::new(((self.bits >> 15) & 1) != 0)
947    }
948    ///Bit 16 - Discontinuous mode
949    #[inline(always)]
950    pub fn discen(&self) -> DISCEN_R {
951        DISCEN_R::new(((self.bits >> 16) & 1) != 0)
952    }
953    ///Bit 22 - Enable the watchdog on a single channel or on all channels
954    #[inline(always)]
955    pub fn awdsgl(&self) -> AWDSGL_R {
956        AWDSGL_R::new(((self.bits >> 22) & 1) != 0)
957    }
958    ///Bit 23 - Analog watchdog enable
959    #[inline(always)]
960    pub fn awden(&self) -> AWDEN_R {
961        AWDEN_R::new(((self.bits >> 23) & 1) != 0)
962    }
963    ///Bits 26:30 - Analog watchdog channel selection
964    #[inline(always)]
965    pub fn awdch(&self) -> AWDCH_R {
966        AWDCH_R::new(((self.bits >> 26) & 0x1f) as u8)
967    }
968}
969impl core::fmt::Debug for R {
970    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
971        f.debug_struct("CFGR1")
972            .field("awdch", &self.awdch())
973            .field("awden", &self.awden())
974            .field("awdsgl", &self.awdsgl())
975            .field("discen", &self.discen())
976            .field("autoff", &self.autoff())
977            .field("wait", &self.wait())
978            .field("cont", &self.cont())
979            .field("ovrmod", &self.ovrmod())
980            .field("exten", &self.exten())
981            .field("extsel", &self.extsel())
982            .field("align", &self.align())
983            .field("res", &self.res())
984            .field("scandir", &self.scandir())
985            .field("dmacfg", &self.dmacfg())
986            .field("dmaen", &self.dmaen())
987            .finish()
988    }
989}
990impl W {
991    ///Bit 0 - Direct memory access enable
992    #[inline(always)]
993    pub fn dmaen(&mut self) -> DMAEN_W<CFGR1rs> {
994        DMAEN_W::new(self, 0)
995    }
996    ///Bit 1 - Direct memery access configuration
997    #[inline(always)]
998    pub fn dmacfg(&mut self) -> DMACFG_W<CFGR1rs> {
999        DMACFG_W::new(self, 1)
1000    }
1001    ///Bit 2 - Scan sequence direction
1002    #[inline(always)]
1003    pub fn scandir(&mut self) -> SCANDIR_W<CFGR1rs> {
1004        SCANDIR_W::new(self, 2)
1005    }
1006    ///Bits 3:4 - Data resolution
1007    #[inline(always)]
1008    pub fn res(&mut self) -> RES_W<CFGR1rs> {
1009        RES_W::new(self, 3)
1010    }
1011    ///Bit 5 - Data alignment
1012    #[inline(always)]
1013    pub fn align(&mut self) -> ALIGN_W<CFGR1rs> {
1014        ALIGN_W::new(self, 5)
1015    }
1016    ///Bits 6:8 - External trigger selection
1017    #[inline(always)]
1018    pub fn extsel(&mut self) -> EXTSEL_W<CFGR1rs> {
1019        EXTSEL_W::new(self, 6)
1020    }
1021    ///Bits 10:11 - External trigger enable and polarity selection
1022    #[inline(always)]
1023    pub fn exten(&mut self) -> EXTEN_W<CFGR1rs> {
1024        EXTEN_W::new(self, 10)
1025    }
1026    ///Bit 12 - Overrun management mode
1027    #[inline(always)]
1028    pub fn ovrmod(&mut self) -> OVRMOD_W<CFGR1rs> {
1029        OVRMOD_W::new(self, 12)
1030    }
1031    ///Bit 13 - Single / continuous conversion mode
1032    #[inline(always)]
1033    pub fn cont(&mut self) -> CONT_W<CFGR1rs> {
1034        CONT_W::new(self, 13)
1035    }
1036    ///Bit 14 - Wait conversion mode
1037    #[inline(always)]
1038    pub fn wait(&mut self) -> WAIT_W<CFGR1rs> {
1039        WAIT_W::new(self, 14)
1040    }
1041    ///Bit 15 - Auto-off mode
1042    #[inline(always)]
1043    pub fn autoff(&mut self) -> AUTOFF_W<CFGR1rs> {
1044        AUTOFF_W::new(self, 15)
1045    }
1046    ///Bit 16 - Discontinuous mode
1047    #[inline(always)]
1048    pub fn discen(&mut self) -> DISCEN_W<CFGR1rs> {
1049        DISCEN_W::new(self, 16)
1050    }
1051    ///Bit 22 - Enable the watchdog on a single channel or on all channels
1052    #[inline(always)]
1053    pub fn awdsgl(&mut self) -> AWDSGL_W<CFGR1rs> {
1054        AWDSGL_W::new(self, 22)
1055    }
1056    ///Bit 23 - Analog watchdog enable
1057    #[inline(always)]
1058    pub fn awden(&mut self) -> AWDEN_W<CFGR1rs> {
1059        AWDEN_W::new(self, 23)
1060    }
1061    ///Bits 26:30 - Analog watchdog channel selection
1062    #[inline(always)]
1063    pub fn awdch(&mut self) -> AWDCH_W<CFGR1rs> {
1064        AWDCH_W::new(self, 26)
1065    }
1066}
1067/**configuration register 1
1068
1069You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1070
1071See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x0.html#ADC:CFGR1)*/
1072pub struct CFGR1rs;
1073impl crate::RegisterSpec for CFGR1rs {
1074    type Ux = u32;
1075}
1076///`read()` method returns [`cfgr1::R`](R) reader structure
1077impl crate::Readable for CFGR1rs {}
1078///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
1079impl crate::Writable for CFGR1rs {
1080    type Safety = crate::Unsafe;
1081}
1082///`reset()` method sets CFGR1 to value 0
1083impl crate::Resettable for CFGR1rs {}
stm32f0/stm32f0x0/adc/cfgr1.rs

stm32f0/stm32f0x0/adc/
cfgr1.rs
