#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFGR1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct AWDCHR {
bits: u8,
}
impl AWDCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `AWDEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AWDENR {
#[doc = "Analog watchdog disabled on regular channels"]
DISABLED,
#[doc = "Analog watchdog enabled on regular channels"]
ENABLED,
}
impl AWDENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AWDENR::DISABLED => false,
AWDENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AWDENR {
match value {
false => AWDENR::DISABLED,
true => AWDENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == AWDENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == AWDENR::ENABLED
}
}
#[doc = "Possible values of the field `AWDSGL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AWDSGLR {
#[doc = "Analog watchdog enabled on all channels"]
ALLCHANNELS,
#[doc = "Analog watchdog enabled on a single channel"]
SINGLECHANNEL,
}
impl AWDSGLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AWDSGLR::ALLCHANNELS => false,
AWDSGLR::SINGLECHANNEL => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AWDSGLR {
match value {
false => AWDSGLR::ALLCHANNELS,
true => AWDSGLR::SINGLECHANNEL,
}
}
#[doc = "Checks if the value of the field is `ALLCHANNELS`"]
#[inline]
pub fn is_all_channels(&self) -> bool {
*self == AWDSGLR::ALLCHANNELS
}
#[doc = "Checks if the value of the field is `SINGLECHANNEL`"]
#[inline]
pub fn is_single_channel(&self) -> bool {
*self == AWDSGLR::SINGLECHANNEL
}
}
#[doc = "Possible values of the field `DISCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DISCENR {
#[doc = "Discontinuous mode on regular channels disabled"]
DISABLED,
#[doc = "Discontinuous mode on regular channels enabled"]
ENABLED,
}
impl DISCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DISCENR::DISABLED => false,
DISCENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DISCENR {
match value {
false => DISCENR::DISABLED,
true => DISCENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == DISCENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == DISCENR::ENABLED
}
}
#[doc = "Possible values of the field `AUTOFF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AUTOFFR {
#[doc = "Auto-off mode disabled"]
DISABLED,
#[doc = "Auto-off mode enabled"]
ENABLED,
}
impl AUTOFFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AUTOFFR::DISABLED => false,
AUTOFFR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AUTOFFR {
match value {
false => AUTOFFR::DISABLED,
true => AUTOFFR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == AUTOFFR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == AUTOFFR::ENABLED
}
}
#[doc = r" Value of the field"]
pub struct AUTDLYR {
bits: bool,
}
impl AUTDLYR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `CONT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CONTR {
#[doc = "Single conversion mode"]
SINGLE,
#[doc = "Continuous conversion mode"]
CONTINUOUS,
}
impl CONTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CONTR::SINGLE => false,
CONTR::CONTINUOUS => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CONTR {
match value {
false => CONTR::SINGLE,
true => CONTR::CONTINUOUS,
}
}
#[doc = "Checks if the value of the field is `SINGLE`"]
#[inline]
pub fn is_single(&self) -> bool {
*self == CONTR::SINGLE
}
#[doc = "Checks if the value of the field is `CONTINUOUS`"]
#[inline]
pub fn is_continuous(&self) -> bool {
*self == CONTR::CONTINUOUS
}
}
#[doc = "Possible values of the field `OVRMOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OVRMODR {
#[doc = "ADC_DR register is preserved with the old data when an overrun is detected"]
PRESERVED,
#[doc = "ADC_DR register is overwritten with the last conversion result when an overrun is detected"]
OVERWRITTEN,
}
impl OVRMODR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
OVRMODR::PRESERVED => false,
OVRMODR::OVERWRITTEN => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> OVRMODR {
match value {
false => OVRMODR::PRESERVED,
true => OVRMODR::OVERWRITTEN,
}
}
#[doc = "Checks if the value of the field is `PRESERVED`"]
#[inline]
pub fn is_preserved(&self) -> bool {
*self == OVRMODR::PRESERVED
}
#[doc = "Checks if the value of the field is `OVERWRITTEN`"]
#[inline]
pub fn is_overwritten(&self) -> bool {
*self == OVRMODR::OVERWRITTEN
}
}
#[doc = "Possible values of the field `EXTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTENR {
#[doc = "Trigger detection disabled"]
DISABLED,
#[doc = "Trigger detection on the rising edge"]
RISINGEDGE,
#[doc = "Trigger detection on the falling edge"]
FALLINGEDGE,
#[doc = "Trigger detection on both the rising and falling edges"]
BOTHEDGES,
}
impl EXTENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EXTENR::DISABLED => 0,
EXTENR::RISINGEDGE => 1,
EXTENR::FALLINGEDGE => 2,
EXTENR::BOTHEDGES => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EXTENR {
match value {
0 => EXTENR::DISABLED,
1 => EXTENR::RISINGEDGE,
2 => EXTENR::FALLINGEDGE,
3 => EXTENR::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == EXTENR::DISABLED
}
#[doc = "Checks if the value of the field is `RISINGEDGE`"]
#[inline]
pub fn is_rising_edge(&self) -> bool {
*self == EXTENR::RISINGEDGE
}
#[doc = "Checks if the value of the field is `FALLINGEDGE`"]
#[inline]
pub fn is_falling_edge(&self) -> bool {
*self == EXTENR::FALLINGEDGE
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline]
pub fn is_both_edges(&self) -> bool {
*self == EXTENR::BOTHEDGES
}
}
#[doc = "Possible values of the field `EXTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EXTSELR {
#[doc = "Timer 2 TRGO event"]
TIM2_TRGO,
#[doc = "Timer 1 TRGO Event"]
TIM1_TRGO,
#[doc = "Timer 1 CC4 event"]
TIM1_CC4,
#[doc = "Timer 3 TRGO event"]
TIM3_TRGO,
#[doc = "Timer 15 TRGO event"]
TIM15_TRGO,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl EXTSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
EXTSELR::TIM2_TRGO => 2,
EXTSELR::TIM1_TRGO => 0,
EXTSELR::TIM1_CC4 => 1,
EXTSELR::TIM3_TRGO => 3,
EXTSELR::TIM15_TRGO => 4,
EXTSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> EXTSELR {
match value {
2 => EXTSELR::TIM2_TRGO,
0 => EXTSELR::TIM1_TRGO,
1 => EXTSELR::TIM1_CC4,
3 => EXTSELR::TIM3_TRGO,
4 => EXTSELR::TIM15_TRGO,
i => EXTSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `TIM2_TRGO`"]
#[inline]
pub fn is_tim2_trgo(&self) -> bool {
*self == EXTSELR::TIM2_TRGO
}
#[doc = "Checks if the value of the field is `TIM1_TRGO`"]
#[inline]
pub fn is_tim1_trgo(&self) -> bool {
*self == EXTSELR::TIM1_TRGO
}
#[doc = "Checks if the value of the field is `TIM1_CC4`"]
#[inline]
pub fn is_tim1_cc4(&self) -> bool {
*self == EXTSELR::TIM1_CC4
}
#[doc = "Checks if the value of the field is `TIM3_TRGO`"]
#[inline]
pub fn is_tim3_trgo(&self) -> bool {
*self == EXTSELR::TIM3_TRGO
}
#[doc = "Checks if the value of the field is `TIM15_TRGO`"]
#[inline]
pub fn is_tim15_trgo(&self) -> bool {
*self == EXTSELR::TIM15_TRGO
}
}
#[doc = "Possible values of the field `ALIGN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALIGNR {
#[doc = "Right alignment"]
RIGHT,
#[doc = "Left alignment"]
LEFT,
}
impl ALIGNR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ALIGNR::RIGHT => false,
ALIGNR::LEFT => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ALIGNR {
match value {
false => ALIGNR::RIGHT,
true => ALIGNR::LEFT,
}
}
#[doc = "Checks if the value of the field is `RIGHT`"]
#[inline]
pub fn is_right(&self) -> bool {
*self == ALIGNR::RIGHT
}
#[doc = "Checks if the value of the field is `LEFT`"]
#[inline]
pub fn is_left(&self) -> bool {
*self == ALIGNR::LEFT
}
}
#[doc = "Possible values of the field `RES`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RESR {
#[doc = "12-bit (14 ADCCLK cycles)"]
TWELVEBIT,
#[doc = "10-bit (13 ADCCLK cycles)"]
TENBIT,
#[doc = "8-bit (11 ADCCLK cycles)"]
EIGHTBIT,
#[doc = "6-bit (9 ADCCLK cycles)"]
SIXBIT,
}
impl RESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
RESR::TWELVEBIT => 0,
RESR::TENBIT => 1,
RESR::EIGHTBIT => 2,
RESR::SIXBIT => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> RESR {
match value {
0 => RESR::TWELVEBIT,
1 => RESR::TENBIT,
2 => RESR::EIGHTBIT,
3 => RESR::SIXBIT,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TWELVEBIT`"]
#[inline]
pub fn is_twelve_bit(&self) -> bool {
*self == RESR::TWELVEBIT
}
#[doc = "Checks if the value of the field is `TENBIT`"]
#[inline]
pub fn is_ten_bit(&self) -> bool {
*self == RESR::TENBIT
}
#[doc = "Checks if the value of the field is `EIGHTBIT`"]
#[inline]
pub fn is_eight_bit(&self) -> bool {
*self == RESR::EIGHTBIT
}
#[doc = "Checks if the value of the field is `SIXBIT`"]
#[inline]
pub fn is_six_bit(&self) -> bool {
*self == RESR::SIXBIT
}
}
#[doc = "Possible values of the field `SCANDIR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCANDIRR {
#[doc = "Upward scan (from CHSEL0 to CHSEL18)"]
UPWARD,
#[doc = "Backward scan (from CHSEL18 to CHSEL0)"]
BACKWARD,
}
impl SCANDIRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SCANDIRR::UPWARD => false,
SCANDIRR::BACKWARD => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SCANDIRR {
match value {
false => SCANDIRR::UPWARD,
true => SCANDIRR::BACKWARD,
}
}
#[doc = "Checks if the value of the field is `UPWARD`"]
#[inline]
pub fn is_upward(&self) -> bool {
*self == SCANDIRR::UPWARD
}
#[doc = "Checks if the value of the field is `BACKWARD`"]
#[inline]
pub fn is_backward(&self) -> bool {
*self == SCANDIRR::BACKWARD
}
}
#[doc = "Possible values of the field `DMACFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMACFGR {
#[doc = "DMA one shot mode"]
ONESHOT,
#[doc = "DMA circular mode"]
CIRCULAR,
}
impl DMACFGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMACFGR::ONESHOT => false,
DMACFGR::CIRCULAR => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMACFGR {
match value {
false => DMACFGR::ONESHOT,
true => DMACFGR::CIRCULAR,
}
}
#[doc = "Checks if the value of the field is `ONESHOT`"]
#[inline]
pub fn is_one_shot(&self) -> bool {
*self == DMACFGR::ONESHOT
}
#[doc = "Checks if the value of the field is `CIRCULAR`"]
#[inline]
pub fn is_circular(&self) -> bool {
*self == DMACFGR::CIRCULAR
}
}
#[doc = "Possible values of the field `DMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAENR {
#[doc = "DMA mode disabled"]
DISABLED,
#[doc = "DMA mode enabled"]
ENABLED,
}
impl DMAENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMAENR::DISABLED => false,
DMAENR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMAENR {
match value {
false => DMAENR::DISABLED,
true => DMAENR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == DMAENR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == DMAENR::ENABLED
}
}
#[doc = "Possible values of the field `WAIT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum WAITR {
#[doc = "Wait conversion mode off"]
DISABLED,
#[doc = "Wait conversion mode on"]
ENABLED,
}
impl WAITR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
WAITR::DISABLED => false,
WAITR::ENABLED => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> WAITR {
match value {
false => WAITR::DISABLED,
true => WAITR::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline]
pub fn is_disabled(&self) -> bool {
*self == WAITR::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline]
pub fn is_enabled(&self) -> bool {
*self == WAITR::ENABLED
}
}
#[doc = r" Proxy"]
pub struct _AWDCHW<'a> {
w: &'a mut W,
}
impl<'a> _AWDCHW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AWDEN`"]
pub enum AWDENW {
#[doc = "Analog watchdog disabled on regular channels"]
DISABLED,
#[doc = "Analog watchdog enabled on regular channels"]
ENABLED,
}
impl AWDENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AWDENW::DISABLED => false,
AWDENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AWDENW<'a> {
w: &'a mut W,
}
impl<'a> _AWDENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AWDENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Analog watchdog disabled on regular channels"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(AWDENW::DISABLED)
}
#[doc = "Analog watchdog enabled on regular channels"]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(AWDENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AWDSGL`"]
pub enum AWDSGLW {
#[doc = "Analog watchdog enabled on all channels"]
ALLCHANNELS,
#[doc = "Analog watchdog enabled on a single channel"]
SINGLECHANNEL,
}
impl AWDSGLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AWDSGLW::ALLCHANNELS => false,
AWDSGLW::SINGLECHANNEL => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AWDSGLW<'a> {
w: &'a mut W,
}
impl<'a> _AWDSGLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AWDSGLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Analog watchdog enabled on all channels"]
#[inline]
pub fn all_channels(self) -> &'a mut W {
self.variant(AWDSGLW::ALLCHANNELS)
}
#[doc = "Analog watchdog enabled on a single channel"]
#[inline]
pub fn single_channel(self) -> &'a mut W {
self.variant(AWDSGLW::SINGLECHANNEL)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DISCEN`"]
pub enum DISCENW {
#[doc = "Discontinuous mode on regular channels disabled"]
DISABLED,
#[doc = "Discontinuous mode on regular channels enabled"]
ENABLED,
}
impl DISCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DISCENW::DISABLED => false,
DISCENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DISCENW<'a> {
w: &'a mut W,
}
impl<'a> _DISCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DISCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Discontinuous mode on regular channels disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(DISCENW::DISABLED)
}
#[doc = "Discontinuous mode on regular channels enabled"]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(DISCENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AUTOFF`"]
pub enum AUTOFFW {
#[doc = "Auto-off mode disabled"]
DISABLED,
#[doc = "Auto-off mode enabled"]
ENABLED,
}
impl AUTOFFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AUTOFFW::DISABLED => false,
AUTOFFW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AUTOFFW<'a> {
w: &'a mut W,
}
impl<'a> _AUTOFFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AUTOFFW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Auto-off mode disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(AUTOFFW::DISABLED)
}
#[doc = "Auto-off mode enabled"]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(AUTOFFW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _AUTDLYW<'a> {
w: &'a mut W,
}
impl<'a> _AUTDLYW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CONT`"]
pub enum CONTW {
#[doc = "Single conversion mode"]
SINGLE,
#[doc = "Continuous conversion mode"]
CONTINUOUS,
}
impl CONTW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CONTW::SINGLE => false,
CONTW::CONTINUOUS => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CONTW<'a> {
w: &'a mut W,
}
impl<'a> _CONTW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CONTW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Single conversion mode"]
#[inline]
pub fn single(self) -> &'a mut W {
self.variant(CONTW::SINGLE)
}
#[doc = "Continuous conversion mode"]
#[inline]
pub fn continuous(self) -> &'a mut W {
self.variant(CONTW::CONTINUOUS)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 13;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `OVRMOD`"]
pub enum OVRMODW {
#[doc = "ADC_DR register is preserved with the old data when an overrun is detected"]
PRESERVED,
#[doc = "ADC_DR register is overwritten with the last conversion result when an overrun is detected"]
OVERWRITTEN,
}
impl OVRMODW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
OVRMODW::PRESERVED => false,
OVRMODW::OVERWRITTEN => true,
}
}
}
#[doc = r" Proxy"]
pub struct _OVRMODW<'a> {
w: &'a mut W,
}
impl<'a> _OVRMODW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: OVRMODW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "ADC_DR register is preserved with the old data when an overrun is detected"]
#[inline]
pub fn preserved(self) -> &'a mut W {
self.variant(OVRMODW::PRESERVED)
}
#[doc = "ADC_DR register is overwritten with the last conversion result when an overrun is detected"]
#[inline]
pub fn overwritten(self) -> &'a mut W {
self.variant(OVRMODW::OVERWRITTEN)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTEN`"]
pub enum EXTENW {
#[doc = "Trigger detection disabled"]
DISABLED,
#[doc = "Trigger detection on the rising edge"]
RISINGEDGE,
#[doc = "Trigger detection on the falling edge"]
FALLINGEDGE,
#[doc = "Trigger detection on both the rising and falling edges"]
BOTHEDGES,
}
impl EXTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EXTENW::DISABLED => 0,
EXTENW::RISINGEDGE => 1,
EXTENW::FALLINGEDGE => 2,
EXTENW::BOTHEDGES => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTENW<'a> {
w: &'a mut W,
}
impl<'a> _EXTENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTENW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Trigger detection disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(EXTENW::DISABLED)
}
#[doc = "Trigger detection on the rising edge"]
#[inline]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTENW::RISINGEDGE)
}
#[doc = "Trigger detection on the falling edge"]
#[inline]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTENW::FALLINGEDGE)
}
#[doc = "Trigger detection on both the rising and falling edges"]
#[inline]
pub fn both_edges(self) -> &'a mut W {
self.variant(EXTENW::BOTHEDGES)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `EXTSEL`"]
pub enum EXTSELW {
#[doc = "Timer 2 TRGO event"]
TIM2_TRGO,
#[doc = "Timer 1 TRGO Event"]
TIM1_TRGO,
#[doc = "Timer 1 CC4 event"]
TIM1_CC4,
#[doc = "Timer 3 TRGO event"]
TIM3_TRGO,
#[doc = "Timer 15 TRGO event"]
TIM15_TRGO,
}
impl EXTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
EXTSELW::TIM2_TRGO => 2,
EXTSELW::TIM1_TRGO => 0,
EXTSELW::TIM1_CC4 => 1,
EXTSELW::TIM3_TRGO => 3,
EXTSELW::TIM15_TRGO => 4,
}
}
}
#[doc = r" Proxy"]
pub struct _EXTSELW<'a> {
w: &'a mut W,
}
impl<'a> _EXTSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EXTSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Timer 2 TRGO event"]
#[inline]
pub fn tim2_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM2_TRGO)
}
#[doc = "Timer 1 TRGO Event"]
#[inline]
pub fn tim1_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_TRGO)
}
#[doc = "Timer 1 CC4 event"]
#[inline]
pub fn tim1_cc4(self) -> &'a mut W {
self.variant(EXTSELW::TIM1_CC4)
}
#[doc = "Timer 3 TRGO event"]
#[inline]
pub fn tim3_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM3_TRGO)
}
#[doc = "Timer 15 TRGO event"]
#[inline]
pub fn tim15_trgo(self) -> &'a mut W {
self.variant(EXTSELW::TIM15_TRGO)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ALIGN`"]
pub enum ALIGNW {
#[doc = "Right alignment"]
RIGHT,
#[doc = "Left alignment"]
LEFT,
}
impl ALIGNW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ALIGNW::RIGHT => false,
ALIGNW::LEFT => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ALIGNW<'a> {
w: &'a mut W,
}
impl<'a> _ALIGNW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ALIGNW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Right alignment"]
#[inline]
pub fn right(self) -> &'a mut W {
self.variant(ALIGNW::RIGHT)
}
#[doc = "Left alignment"]
#[inline]
pub fn left(self) -> &'a mut W {
self.variant(ALIGNW::LEFT)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RES`"]
pub enum RESW {
#[doc = "12-bit (14 ADCCLK cycles)"]
TWELVEBIT,
#[doc = "10-bit (13 ADCCLK cycles)"]
TENBIT,
#[doc = "8-bit (11 ADCCLK cycles)"]
EIGHTBIT,
#[doc = "6-bit (9 ADCCLK cycles)"]
SIXBIT,
}
impl RESW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RESW::TWELVEBIT => 0,
RESW::TENBIT => 1,
RESW::EIGHTBIT => 2,
RESW::SIXBIT => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _RESW<'a> {
w: &'a mut W,
}
impl<'a> _RESW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RESW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "12-bit (14 ADCCLK cycles)"]
#[inline]
pub fn twelve_bit(self) -> &'a mut W {
self.variant(RESW::TWELVEBIT)
}
#[doc = "10-bit (13 ADCCLK cycles)"]
#[inline]
pub fn ten_bit(self) -> &'a mut W {
self.variant(RESW::TENBIT)
}
#[doc = "8-bit (11 ADCCLK cycles)"]
#[inline]
pub fn eight_bit(self) -> &'a mut W {
self.variant(RESW::EIGHTBIT)
}
#[doc = "6-bit (9 ADCCLK cycles)"]
#[inline]
pub fn six_bit(self) -> &'a mut W {
self.variant(RESW::SIXBIT)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SCANDIR`"]
pub enum SCANDIRW {
#[doc = "Upward scan (from CHSEL0 to CHSEL18)"]
UPWARD,
#[doc = "Backward scan (from CHSEL18 to CHSEL0)"]
BACKWARD,
}
impl SCANDIRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SCANDIRW::UPWARD => false,
SCANDIRW::BACKWARD => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SCANDIRW<'a> {
w: &'a mut W,
}
impl<'a> _SCANDIRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SCANDIRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Upward scan (from CHSEL0 to CHSEL18)"]
#[inline]
pub fn upward(self) -> &'a mut W {
self.variant(SCANDIRW::UPWARD)
}
#[doc = "Backward scan (from CHSEL18 to CHSEL0)"]
#[inline]
pub fn backward(self) -> &'a mut W {
self.variant(SCANDIRW::BACKWARD)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMACFG`"]
pub enum DMACFGW {
#[doc = "DMA one shot mode"]
ONESHOT,
#[doc = "DMA circular mode"]
CIRCULAR,
}
impl DMACFGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMACFGW::ONESHOT => false,
DMACFGW::CIRCULAR => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMACFGW<'a> {
w: &'a mut W,
}
impl<'a> _DMACFGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMACFGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA one shot mode"]
#[inline]
pub fn one_shot(self) -> &'a mut W {
self.variant(DMACFGW::ONESHOT)
}
#[doc = "DMA circular mode"]
#[inline]
pub fn circular(self) -> &'a mut W {
self.variant(DMACFGW::CIRCULAR)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMAEN`"]
pub enum DMAENW {
#[doc = "DMA mode disabled"]
DISABLED,
#[doc = "DMA mode enabled"]
ENABLED,
}
impl DMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMAENW::DISABLED => false,
DMAENW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMAENW<'a> {
w: &'a mut W,
}
impl<'a> _DMAENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA mode disabled"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(DMAENW::DISABLED)
}
#[doc = "DMA mode enabled"]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(DMAENW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `WAIT`"]
pub enum WAITW {
#[doc = "Wait conversion mode off"]
DISABLED,
#[doc = "Wait conversion mode on"]
ENABLED,
}
impl WAITW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
WAITW::DISABLED => false,
WAITW::ENABLED => true,
}
}
}
#[doc = r" Proxy"]
pub struct _WAITW<'a> {
w: &'a mut W,
}
impl<'a> _WAITW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: WAITW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Wait conversion mode off"]
#[inline]
pub fn disabled(self) -> &'a mut W {
self.variant(WAITW::DISABLED)
}
#[doc = "Wait conversion mode on"]
#[inline]
pub fn enabled(self) -> &'a mut W {
self.variant(WAITW::ENABLED)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 14;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 26:30 - Analog watchdog channel selection"]
#[inline]
pub fn awdch(&self) -> AWDCHR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) as u8
};
AWDCHR { bits }
}
#[doc = "Bit 23 - Analog watchdog enable"]
#[inline]
pub fn awden(&self) -> AWDENR {
AWDENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Enable the watchdog on a single channel or on all channels"]
#[inline]
pub fn awdsgl(&self) -> AWDSGLR {
AWDSGLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - Discontinuous mode"]
#[inline]
pub fn discen(&self) -> DISCENR {
DISCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 15 - Auto-off mode"]
#[inline]
pub fn autoff(&self) -> AUTOFFR {
AUTOFFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Auto-delayed conversion mode"]
#[inline]
pub fn autdly(&self) -> AUTDLYR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
};
AUTDLYR { bits }
}
#[doc = "Bit 13 - Single / continuous conversion mode"]
#[inline]
pub fn cont(&self) -> CONTR {
CONTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 12 - Overrun management mode"]
#[inline]
pub fn ovrmod(&self) -> OVRMODR {
OVRMODR::_from({
const MASK: bool = true;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 10:11 - External trigger enable and polarity selection"]
#[inline]
pub fn exten(&self) -> EXTENR {
EXTENR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 6:8 - External trigger selection"]
#[inline]
pub fn extsel(&self) -> EXTSELR {
EXTSELR::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 5 - Data alignment"]
#[inline]
pub fn align(&self) -> ALIGNR {
ALIGNR::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 3:4 - Data resolution"]
#[inline]
pub fn res(&self) -> RESR {
RESR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Scan sequence direction"]
#[inline]
pub fn scandir(&self) -> SCANDIRR {
SCANDIRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Direct memery access configuration"]
#[inline]
pub fn dmacfg(&self) -> DMACFGR {
DMACFGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 0 - Direct memory access enable"]
#[inline]
pub fn dmaen(&self) -> DMAENR {
DMAENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 14 - Wait conversion mode"]
#[inline]
pub fn wait(&self) -> WAITR {
WAITR::_from({
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 26:30 - Analog watchdog channel selection"]
#[inline]
pub fn awdch(&mut self) -> _AWDCHW {
_AWDCHW { w: self }
}
#[doc = "Bit 23 - Analog watchdog enable"]
#[inline]
pub fn awden(&mut self) -> _AWDENW {
_AWDENW { w: self }
}
#[doc = "Bit 22 - Enable the watchdog on a single channel or on all channels"]
#[inline]
pub fn awdsgl(&mut self) -> _AWDSGLW {
_AWDSGLW { w: self }
}
#[doc = "Bit 16 - Discontinuous mode"]
#[inline]
pub fn discen(&mut self) -> _DISCENW {
_DISCENW { w: self }
}
#[doc = "Bit 15 - Auto-off mode"]
#[inline]
pub fn autoff(&mut self) -> _AUTOFFW {
_AUTOFFW { w: self }
}
#[doc = "Bit 14 - Auto-delayed conversion mode"]
#[inline]
pub fn autdly(&mut self) -> _AUTDLYW {
_AUTDLYW { w: self }
}
#[doc = "Bit 13 - Single / continuous conversion mode"]
#[inline]
pub fn cont(&mut self) -> _CONTW {
_CONTW { w: self }
}
#[doc = "Bit 12 - Overrun management mode"]
#[inline]
pub fn ovrmod(&mut self) -> _OVRMODW {
_OVRMODW { w: self }
}
#[doc = "Bits 10:11 - External trigger enable and polarity selection"]
#[inline]
pub fn exten(&mut self) -> _EXTENW {
_EXTENW { w: self }
}
#[doc = "Bits 6:8 - External trigger selection"]
#[inline]
pub fn extsel(&mut self) -> _EXTSELW {
_EXTSELW { w: self }
}
#[doc = "Bit 5 - Data alignment"]
#[inline]
pub fn align(&mut self) -> _ALIGNW {
_ALIGNW { w: self }
}
#[doc = "Bits 3:4 - Data resolution"]
#[inline]
pub fn res(&mut self) -> _RESW {
_RESW { w: self }
}
#[doc = "Bit 2 - Scan sequence direction"]
#[inline]
pub fn scandir(&mut self) -> _SCANDIRW {
_SCANDIRW { w: self }
}
#[doc = "Bit 1 - Direct memery access configuration"]
#[inline]
pub fn dmacfg(&mut self) -> _DMACFGW {
_DMACFGW { w: self }
}
#[doc = "Bit 0 - Direct memory access enable"]
#[inline]
pub fn dmaen(&mut self) -> _DMAENW {
_DMAENW { w: self }
}
#[doc = "Bit 14 - Wait conversion mode"]
#[inline]
pub fn wait(&mut self) -> _WAITW {
_WAITW { w: self }
}
}