Module stm32_hal2::pac::wwdg1::cr

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Expand description

Control register

Structs§

  • CR_SPEC
    Control register
  • R
    Register CR reader
  • W
    Register CR writer

Enums§

  • WDGA_A
    Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset.

Type Aliases§

  • T_R
    Field T reader - 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
  • T_W
    Field T writer - 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
  • WDGA_R
    Field WDGA reader - Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset.
  • WDGA_W
    Field WDGA writer - Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset.