Module stm32_hal2::pac::spi1::cr1

control register 1

Structs

• CR1_SPEC
  control register 1
• R
  Register CR1 reader
• W
  Register CR1 writer

Enums

• CRC33_17_A
  32-bit CRC polynomial configuration
• CSTART_A
  Master transfer start
• CSUSP_AW
  Master SUSPend request
• HDDIR_A
  Rx/Tx direction at Half-duplex mode
• IOLOCK_A
  Locking the AF configuration of associated IOs
• MASRX_A
  Master automatic SUSP in Receive mode
• RCRCINI_A
  CRC calculation initialization pattern control for receiver
• SPE_A
  Serial Peripheral Enable
• SSI_A
  Internal SS signal input level
• TCRCINI_A
  CRC calculation initialization pattern control for transmitter

Type Aliases

• CRC33_17_R
  Field CRC33_17 reader - 32-bit CRC polynomial configuration
• CRC33_17_W
  Field CRC33_17 writer - 32-bit CRC polynomial configuration
• CSTART_R
  Field CSTART reader - Master transfer start
• CSTART_W
  Field CSTART writer - Master transfer start
• CSUSP_W
  Field CSUSP writer - Master SUSPend request
• HDDIR_R
  Field HDDIR reader - Rx/Tx direction at Half-duplex mode
• HDDIR_W
  Field HDDIR writer - Rx/Tx direction at Half-duplex mode
• IOLOCK_R
  Field IOLOCK reader - Locking the AF configuration of associated IOs
• MASRX_R
  Field MASRX reader - Master automatic SUSP in Receive mode
• MASRX_W
  Field MASRX writer - Master automatic SUSP in Receive mode
• RCRCINI_R
  Field RCRCINI reader - CRC calculation initialization pattern control for receiver
• RCRCINI_W
  Field RCRCINI writer - CRC calculation initialization pattern control for receiver
• SPE_R
  Field SPE reader - Serial Peripheral Enable
• SPE_W
  Field SPE writer - Serial Peripheral Enable
• SSI_R
  Field SSI reader - Internal SS signal input level
• SSI_W
  Field SSI writer - Internal SS signal input level
• TCRCINI_R
  Field TCRCINI reader - CRC calculation initialization pattern control for transmitter
• TCRCINI_W
  Field TCRCINI writer - CRC calculation initialization pattern control for transmitter