Module stm32_hal2::pac::spi1::cfg2
source · Expand description
configuration register 2
Structs§
- configuration register 2
- Register
CFG2reader - Register
CFG2writer
Enums§
- Alternate function GPIOs control
- SPI Communication Mode
- Clock phase
- Clock polarity
- Swap functionality of MISO and MOSI pins
- Data frame format
- SPI Master
- Serial Protocol
- SS input/output polarity
- Software management of SS signal input
- SS output enable
- SS output management in master mode
Type Aliases§
- Field
AFCNTRreader - Alternate function GPIOs control - Field
AFCNTRwriter - Alternate function GPIOs control - Field
COMMreader - SPI Communication Mode - Field
COMMwriter - SPI Communication Mode - Field
CPHAreader - Clock phase - Field
CPHAwriter - Clock phase - Field
CPOLreader - Clock polarity - Field
CPOLwriter - Clock polarity - Field
IOSWPreader - Swap functionality of MISO and MOSI pins - Field
IOSWPwriter - Swap functionality of MISO and MOSI pins - Field
LSBFRSTreader - Data frame format - Field
LSBFRSTwriter - Data frame format - Field
MASTERreader - SPI Master - Field
MASTERwriter - SPI Master - Field
MIDIreader - Master Inter-Data Idleness - Field
MIDIwriter - Master Inter-Data Idleness - Field
MSSIreader - Master SS Idleness - Field
MSSIwriter - Master SS Idleness - Field
SPreader - Serial Protocol - Field
SPwriter - Serial Protocol - Field
SSIOPreader - SS input/output polarity - Field
SSIOPwriter - SS input/output polarity - Field
SSMreader - Software management of SS signal input - Field
SSMwriter - Software management of SS signal input - Field
SSOEreader - SS output enable - Field
SSOEwriter - SS output enable - Field
SSOMreader - SS output management in master mode - Field
SSOMwriter - SS output management in master mode