Module stm32_hal2::pac::sdmmc1::idmactrlr

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Structs

• IDMACTRLR_SPEC
  The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
• R
  Register IDMACTRLR reader
• W
  Register IDMACTRLR writer

Type Aliases

• IDMABACT_R
  Field IDMABACT reader - Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.
• IDMABACT_W
  Field IDMABACT writer - Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.
• IDMABMODE_R
  Field IDMABMODE reader - Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
• IDMABMODE_W
  Field IDMABMODE writer - Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
• IDMAEN_R
  Field IDMAEN reader - IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
• IDMAEN_W
  Field IDMAEN writer - IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).