Module stm32_hal2::pac::sdmmc1::idmabase1r

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Structs

• IDMABASE1R_SPEC
  The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.
• R
  Register IDMABASE1R reader
• W
  Register IDMABASE1R writer

Type Aliases

• IDMABASE1_R
  Field IDMABASE1 reader - Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).
• IDMABASE1_W
  Field IDMABASE1 writer - Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).