Module stm32_hal2::pac::rng::sr

RNG status register

Structs

• R
  Register SR reader
• SR_SPEC
  RNG status register
• W
  Register SR writer

Type Aliases

• CECS_R
  Field CECS reader - Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
• CEIS_R
  Field CEIS reader - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
• CEIS_W
  Field CEIS writer - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
• DRDY_R
  Field DRDY reader - Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated.
• SECS_R
  Field SECS reader - Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101…01)
• SEIS_R
  Field SEIS reader - Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101…01) An interrupt is pending if IE = 1 in the RNG_CR register.
• SEIS_W
  Field SEIS writer - Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101…01) An interrupt is pending if IE = 1 in the RNG_CR register.