Module stm32_hal2::pac::i2c1::oar1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Structs

• OAR1_SPEC
  Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
• R
  Register OAR1 reader
• W
  Register OAR1 writer

Enums

• OA1EN_A
  Own Address 1 enable
• OA1MODE_A
  Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.

Type Aliases

• OA1EN_R
  Field OA1EN reader - Own Address 1 enable
• OA1EN_W
  Field OA1EN writer - Own Address 1 enable
• OA1MODE_R
  Field OA1MODE reader - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
• OA1MODE_W
  Field OA1MODE writer - Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
• OA1_R
  Field OA1 reader - Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0.
• OA1_W
  Field OA1 writer - Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0.