Module stm32_hal2::pac::i2c1::cr1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Structs

• CR1_SPEC
  Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
• R
  Register CR1 reader
• W
  Register CR1 writer

Enums

• ADDRIE_A
  Address match Interrupt enable (slave only)
• ALERTEN_A
  SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• ANFOFF_A
  Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• DNF_A
  Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]
• ERRIE_A
  Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
• GCEN_A
  General call enable
• NACKIE_A
  Not acknowledge received Interrupt enable
• NOSTRETCH_A
  Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• PECEN_A
  PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• PE_A
  Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
• RXDMAEN_A
  DMA reception requests enable
• RXIE_A
  RX Interrupt enable
• SBC_A
  Slave byte control This bit is used to enable hardware byte control in slave mode.
• SMBDEN_A
  SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• SMBHEN_A
  SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• STOPIE_A
  STOP detection Interrupt enable
• TCIE_A
  Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
• TXDMAEN_A
  DMA transmission requests enable
• TXIE_A
  TX Interrupt enable
• WUPEN_A
  Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000

Type Aliases

• ADDRIE_R
  Field ADDRIE reader - Address match Interrupt enable (slave only)
• ADDRIE_W
  Field ADDRIE writer - Address match Interrupt enable (slave only)
• ALERTEN_R
  Field ALERTEN reader - SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• ALERTEN_W
  Field ALERTEN writer - SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• ANFOFF_R
  Field ANFOFF reader - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• ANFOFF_W
  Field ANFOFF writer - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• DNF_R
  Field DNF reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]
• DNF_W
  Field DNF writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]
• ERRIE_R
  Field ERRIE reader - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
• ERRIE_W
  Field ERRIE writer - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
• GCEN_R
  Field GCEN reader - General call enable
• GCEN_W
  Field GCEN writer - General call enable
• NACKIE_R
  Field NACKIE reader - Not acknowledge received Interrupt enable
• NACKIE_W
  Field NACKIE writer - Not acknowledge received Interrupt enable
• NOSTRETCH_R
  Field NOSTRETCH reader - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• NOSTRETCH_W
  Field NOSTRETCH writer - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
• PECEN_R
  Field PECEN reader - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• PECEN_W
  Field PECEN writer - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• PE_R
  Field PE reader - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
• PE_W
  Field PE writer - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
• RXDMAEN_R
  Field RXDMAEN reader - DMA reception requests enable
• RXDMAEN_W
  Field RXDMAEN writer - DMA reception requests enable
• RXIE_R
  Field RXIE reader - RX Interrupt enable
• RXIE_W
  Field RXIE writer - RX Interrupt enable
• SBC_R
  Field SBC reader - Slave byte control This bit is used to enable hardware byte control in slave mode.
• SBC_W
  Field SBC writer - Slave byte control This bit is used to enable hardware byte control in slave mode.
• SMBDEN_R
  Field SMBDEN reader - SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• SMBDEN_W
  Field SMBDEN writer - SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• SMBHEN_R
  Field SMBHEN reader - SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• SMBHEN_W
  Field SMBHEN writer - SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation.
• STOPIE_R
  Field STOPIE reader - STOP detection Interrupt enable
• STOPIE_W
  Field STOPIE writer - STOP detection Interrupt enable
• TCIE_R
  Field TCIE reader - Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
• TCIE_W
  Field TCIE writer - Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
• TXDMAEN_R
  Field TXDMAEN reader - DMA transmission requests enable
• TXDMAEN_W
  Field TXDMAEN writer - DMA transmission requests enable
• TXIE_R
  Field TXIE reader - TX Interrupt enable
• TXIE_W
  Field TXIE writer - TX Interrupt enable
• WUPEN_R
  Field WUPEN reader - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000
• WUPEN_W
  Field WUPEN writer - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000