Module stm32_hal2::pac::fmc::sr

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Structs

• R
  Register SR reader
• SR_SPEC
  This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
• W
  Register SR writer

Type Aliases

• FEMPT_R
  Field FEMPT reader - FIFO empty. Read-only bit that provides the status of the FIFO
• IFEN_R
  Field IFEN reader - Interrupt falling edge detection enable bit
• IFEN_W
  Field IFEN writer - Interrupt falling edge detection enable bit
• IFS_R
  Field IFS reader - Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
• IFS_W
  Field IFS writer - Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
• ILEN_R
  Field ILEN reader - Interrupt high-level detection enable bit
• ILEN_W
  Field ILEN writer - Interrupt high-level detection enable bit
• ILS_R
  Field ILS reader - Interrupt high-level status The flag is set by hardware and reset by software.
• ILS_W
  Field ILS writer - Interrupt high-level status The flag is set by hardware and reset by software.
• IREN_R
  Field IREN reader - Interrupt rising edge detection enable bit
• IREN_W
  Field IREN writer - Interrupt rising edge detection enable bit
• IRS_R
  Field IRS reader - Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.
• IRS_W
  Field IRS writer - Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set.