Module stm32_hal2::pac::fmc::sdbank::sdcr

This register contains the control parameters for each SDRAM memory bank

Structs

• R
  Register SDCR reader
• SDCR_SPEC
  This register contains the control parameters for each SDRAM memory bank
• W
  Register SDCR writer

Type Aliases

• CAS_R
  Field CAS reader - CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles
• CAS_W
  Field CAS writer - CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles
• MWID_R
  Field MWID reader - Memory data bus width. These bits define the memory device width.
• MWID_W
  Field MWID writer - Memory data bus width. These bits define the memory device width.
• NB_R
  Field NB reader - Number of internal banks This bit sets the number of internal banks.
• NB_W
  Field NB writer - Number of internal banks This bit sets the number of internal banks.
• NC_R
  Field NC reader - Number of column address bits These bits define the number of bits of a column address.
• NC_W
  Field NC writer - Number of column address bits These bits define the number of bits of a column address.
• NR_R
  Field NR reader - Number of row address bits These bits define the number of bits of a row address.
• NR_W
  Field NR writer - Number of row address bits These bits define the number of bits of a row address.
• RBURST_R
  Field RBURST reader - Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only.
• RBURST_W
  Field RBURST writer - Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only.
• RPIPE_R
  Field RPIPE reader - Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.
• RPIPE_W
  Field RPIPE writer - Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.
• SDCLK_R
  Field SDCLK reader - SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only.
• SDCLK_W
  Field SDCLK writer - SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only.
• WP_R
  Field WP reader - Write protection This bit enables write mode access to the SDRAM bank.
• WP_W
  Field WP writer - Write protection This bit enables write mode access to the SDRAM bank.