Module stm32_hal2::pac::fmc::pcr

NAND Flash control registers

Structs

• PCR_SPEC
  NAND Flash control registers
• R
  Register PCR reader
• W
  Register PCR writer

Type Aliases

• ECCEN_R
  Field ECCEN reader - ECC computation logic enable bit
• ECCEN_W
  Field ECCEN writer - ECC computation logic enable bit
• ECCPS_R
  Field ECCPS reader - ECC page size. These bits define the page size for the extended ECC:
• ECCPS_W
  Field ECCPS writer - ECC page size. These bits define the page size for the extended ECC:
• PBKEN_R
  Field PBKEN reader - NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus
• PBKEN_W
  Field PBKEN writer - NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus
• PWAITEN_R
  Field PWAITEN reader - Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:
• PWAITEN_W
  Field PWAITEN writer - Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:
• PWID_R
  Field PWID reader - Data bus width. These bits define the external memory device width.
• PWID_W
  Field PWID writer - Data bus width. These bits define the external memory device width.
• TAR_R
  Field TAR reader - ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.
• TAR_W
  Field TAR writer - ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.
• TCLR_R
  Field TCLR reader - CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.
• TCLR_W
  Field TCLR writer - CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space.