Type Alias stm32_hal2::pac::fmc::btr1::ADDHLD_W

pub type ADDHLD_W<'a, const O: u8> = FieldWriterRaw<'a, u32, BTR1_SPEC, u8, u8, Unsafe, 4, O>;

Field ADDHLD writer - Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

Aliased Type

struct ADDHLD_W<'a, const O: u8> { /* private fields */ }