Module stm32_hal2::pac::ethernet_mac::macl3l4c0r

L3 and L4 control 0 register

Structs

• MACL3L4C0R_SPEC
  L3 and L4 control 0 register
• R
  Register MACL3L4C0R reader
• W
  Register MACL3L4C0R writer

Type Aliases

• L3DAIM0_R
  Field L3DAIM0 reader - Layer 3 IP DA Inverse Match Enable
• L3DAIM0_W
  Field L3DAIM0 writer - Layer 3 IP DA Inverse Match Enable
• L3DAM0_R
  Field L3DAM0 reader - Layer 3 IP DA Match Enable
• L3DAM0_W
  Field L3DAM0 writer - Layer 3 IP DA Match Enable
• L3HDBM0_R
  Field L3HDBM0 reader - Layer 3 IP DA Higher Bits Match
• L3HDBM0_W
  Field L3HDBM0 writer - Layer 3 IP DA Higher Bits Match
• L3HSBM0_R
  Field L3HSBM0 reader - Layer 3 IP SA Higher Bits Match
• L3HSBM0_W
  Field L3HSBM0 writer - Layer 3 IP SA Higher Bits Match
• L3PEN0_R
  Field L3PEN0 reader - Layer 3 Protocol Enable
• L3PEN0_W
  Field L3PEN0 writer - Layer 3 Protocol Enable
• L3SAIM0_R
  Field L3SAIM0 reader - Layer 3 IP SA Inverse Match Enable
• L3SAIM0_W
  Field L3SAIM0 writer - Layer 3 IP SA Inverse Match Enable
• L3SAM0_R
  Field L3SAM0 reader - Layer 3 IP SA Match Enable
• L3SAM0_W
  Field L3SAM0 writer - Layer 3 IP SA Match Enable
• L4DPIM0_R
  Field L4DPIM0 reader - Layer 4 Destination Port Inverse Match Enable
• L4DPIM0_W
  Field L4DPIM0 writer - Layer 4 Destination Port Inverse Match Enable
• L4DPM0_R
  Field L4DPM0 reader - Layer 4 Destination Port Match Enable
• L4DPM0_W
  Field L4DPM0 writer - Layer 4 Destination Port Match Enable
• L4PEN0_R
  Field L4PEN0 reader - Layer 4 Protocol Enable
• L4PEN0_W
  Field L4PEN0 writer - Layer 4 Protocol Enable
• L4SPIM0_R
  Field L4SPIM0 reader - Layer 4 Source Port Inverse Match Enable
• L4SPIM0_W
  Field L4SPIM0 writer - Layer 4 Source Port Inverse Match Enable
• L4SPM0_R
  Field L4SPM0 reader - Layer 4 Source Port Match Enable
• L4SPM0_W
  Field L4SPM0 writer - Layer 4 Source Port Match Enable