Module stm32_hal2::pac::dma2d::amtcr

DMA2D AXI master timer configuration register

Structs

• AMTCR_SPEC
  DMA2D AXI master timer configuration register
• R
  Register AMTCR reader
• W
  Register AMTCR writer

Enums

• EN_A
  Enable Enables the dead time functionality.

Type Aliases

• DT_R
  Field DT reader - Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.
• DT_W
  Field DT writer - Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.
• EN_R
  Field EN reader - Enable Enables the dead time functionality.
• EN_W
  Field EN writer - Enable Enables the dead time functionality.