Type Definition stm32_hal2::pac::sdmmc1::idmabase1r::IDMABASE1_R
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Field IDMABASE1
reader - Buffer 1 memory base address, shall be word aligned (bit [1:0]
are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0).