Type Definition stm32_hal2::pac::sdmmc1::idmabase0r::IDMABASE0_W

pub type IDMABASE0_W<'a, const O: u8> = FieldWriterRaw<'a, u32, IDMABASE0R_SPEC, u32, u32, Unsafe, 32, O>;

Field IDMABASE0 writer - Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1).