Type Definition stm32_hal2::pac::sdmmc1::clkcr::DDR_W

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pub type DDR_W<'a, const O: u8> = BitWriterRaw<'a, u32, CLKCR_SPEC, bool, BitM, O>;
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Field DDR writer - Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)