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#![no_std]
pub use stm32f4xx_hal as hal;
pub use stm32f4xx_hal::stm32;
use stm32f4xx_hal::stm32::{ETHERNET_MAC, ETHERNET_DMA, NVIC, Interrupt};
pub mod phy;
use phy::{Phy, PhyStatus};
mod smi;
mod ring;
pub use ring::RingEntry;
mod desc;
mod rx;
use rx::{RxRing, RxRingEntry, RxPacket};
pub use rx::{RxDescriptor, RxError};
mod tx;
use tx::{TxRing, TxRingEntry};
pub use tx::{TxDescriptor, TxError};
mod setup;
pub use setup::setup;
#[cfg(feature = "nucleo-f429zi")]
pub use setup::setup_pins;
#[cfg(feature = "smoltcp-phy")]
pub use smoltcp;
#[cfg(feature = "smoltcp-phy")]
mod smoltcp_phy;
#[cfg(feature = "smoltcp-phy")]
pub use smoltcp_phy::{EthRxToken, EthTxToken};
const PHY_ADDR: u8 = 0;
const MTU: usize = 1522;
#[allow(dead_code)]
mod consts {
pub const ETH_MACMIIAR_CR_HCLK_DIV_42: u8 = 0;
pub const ETH_MACMIIAR_CR_HCLK_DIV_62: u8 = 1;
pub const ETH_MACMIIAR_CR_HCLK_DIV_16: u8 = 2;
pub const ETH_MACMIIAR_CR_HCLK_DIV_26: u8 = 3;
pub const ETH_MACMIIAR_CR_HCLK_DIV_102: u8 = 4;
}
use self::consts::*;
pub struct Eth<'rx, 'tx> {
eth_mac: ETHERNET_MAC,
eth_dma: ETHERNET_DMA,
rx_ring: RxRing<'rx>,
tx_ring: TxRing<'tx>,
}
impl<'rx, 'tx> Eth<'rx, 'tx> {
pub fn new(
eth_mac: ETHERNET_MAC, eth_dma: ETHERNET_DMA,
rx_buffer: &'rx mut [RxRingEntry], tx_buffer: &'tx mut [TxRingEntry]
) -> Self {
let mut eth = Eth {
eth_mac,
eth_dma,
rx_ring: RxRing::new(rx_buffer),
tx_ring: TxRing::new(tx_buffer),
};
eth.init();
eth.rx_ring.start(ð.eth_dma);
eth.tx_ring.start(ð.eth_dma);
eth
}
fn init(&mut self) -> &Self {
self.reset_dma_and_wait();
let clock_range = ETH_MACMIIAR_CR_HCLK_DIV_16;
self.eth_mac.macmiiar.modify(|_, w| unsafe { w.cr().bits(clock_range) });
self.get_phy()
.reset()
.set_autoneg();
self.eth_mac.maccr.modify(|_, w| {
w.cstf().set_bit()
.fes().set_bit()
.dm().set_bit()
.apcs().set_bit()
.rd().set_bit()
.re().set_bit()
.te().set_bit()
});
self.eth_mac.macffr.modify(|_, w| {
w.ra().set_bit()
.pm().set_bit()
});
self.eth_mac.macfcr.modify(|_, w| {
w.pt().bits(0x100)
});
self.eth_dma.dmaomr.modify(|_, w| {
w.dtcefd().set_bit()
.rsf().set_bit()
.dfrf().set_bit()
.tsf().set_bit()
.fef().set_bit()
.osf().set_bit()
});
self.eth_dma.dmabmr.modify(|_, w| unsafe {
w.aab().set_bit()
.fb().set_bit()
.rdp().bits(32)
.pbl().bits(32)
.pm().bits(0b01)
.usp().set_bit()
});
self
}
fn reset_dma_and_wait(&self) {
self.eth_dma.dmabmr.modify(|_, w| w.sr().set_bit());
while self.eth_dma.dmabmr.read().sr().bit_is_set() {}
}
pub fn enable_interrupt(&self, nvic: &mut NVIC) {
self.eth_dma.dmaier.modify(|_, w|
w
.nise().set_bit()
.rie().set_bit()
.tie().set_bit()
);
let interrupt = Interrupt::ETH;
nvic.enable(interrupt);
}
pub fn interrupt_handler(&self) {
eth_interrupt_handler(&self.eth_dma);
}
pub fn get_phy<'a>(&'a self) -> Phy<'a> {
Phy::new(&self.eth_mac.macmiiar, &self.eth_mac.macmiidr, PHY_ADDR)
}
pub fn status(&self) -> PhyStatus {
self.get_phy().status()
}
pub fn rx_is_running(&self) -> bool {
self.rx_ring.running_state(&self.eth_dma).is_running()
}
pub fn recv_next(&mut self) -> Result<RxPacket, RxError> {
self.rx_ring.recv_next(&self.eth_dma)
}
pub fn tx_is_running(&self) -> bool {
self.tx_ring.is_running(&self.eth_dma)
}
pub fn send<F: FnOnce(&mut [u8]) -> R, R>(&mut self, length: usize, f: F) -> Result<R, TxError> {
let result = self.tx_ring.send(length, f);
self.tx_ring.demand_poll(&self.eth_dma);
result
}
}
pub fn eth_interrupt_handler(eth_dma: ÐERNET_DMA) {
eth_dma.dmasr.write(|w|
w
.nis().set_bit()
.rs().set_bit()
.ts().set_bit()
);
}