Enum SysReg 

#[non_exhaustive]
pub enum SysReg {
    SctlrEl1,
    Ttbr0El1,
    Ttbr1El1,
    MairEl1,
    AmairEl1,
    TcrEl1,
    SpEl1,
    ElrEl1,
    SpsrEl1,
    VbarEl1,
    IdAa64Mmfr0El1,
    IdAa64Mmfr1El1,
    IdAa64Pfr0El1,
    IdAa64Pfr1El1,
    IdAa64Dfr0El1,
    IdAa64Isar0El1,
    IdAa64Isar1El1,
    MpidrEl1,
    CntvCtlEl0,
    CntvCvalEl0,
    CntvOffEl2,
    CntFrqEl0,
    CntKctlEl1,
    CntpCtlEl0,
    CntpCvalEl0,
    PmCcntrEl0,
    PmCcfiltrEl0,
    PmUserEnrEl0,
    PmCrEl0,
    PmCntEnSetEl0,
    PmOvsSetEl0,
    PmSelrEl0,
    EsrEl1,
    FarEl1,
    Afsr0El1,
    Afsr1El1,
    ContextIdrEl1,
    TpidrEl0,
    TpidrroEl0,
    TpidrEl1,
    ParEl1,
    Fpcr,
    Fpsr,
    CpacrEl1,
    MdscrEl1,
    OslarEl1,
    OsdlrEl1,
}

Sysreg enum — #[non_exhaustive] because the full curated list is iterative.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

SctlrEl1

SCTLR_EL1 — system control register, EL1.

Ttbr0El1

TTBR0_EL1 — translation table base, EL1.

Ttbr1El1

TTBR1_EL1 — translation table base 1, EL1.

MairEl1

MAIR_EL1 — memory attribute indirection register.

AmairEl1

AMAIR_EL1 — auxiliary memory attribute indirection register.

TcrEl1

TCR_EL1 — translation control register.

SpEl1

SP_EL1.

ElrEl1

ELR_EL1 — exception link register.

SpsrEl1

SPSR_EL1 — saved program status register.

VbarEl1

VBAR_EL1 — vector base address register.

IdAa64Mmfr0El1

ID_AA64MMFR0_EL1 — memory model feature register 0.

IdAa64Mmfr1El1

ID_AA64MMFR1_EL1 — memory model feature register 1.

IdAa64Pfr0El1

ID_AA64PFR0_EL1 — processor feature register 0.

IdAa64Pfr1El1

ID_AA64PFR1_EL1 — processor feature register 1.

IdAa64Dfr0El1

ID_AA64DFR0_EL1 — debug feature register 0.

IdAa64Isar0El1

ID_AA64ISAR0_EL1 — instruction set attribute register 0.

IdAa64Isar1El1

ID_AA64ISAR1_EL1 — instruction set attribute register 1.

MpidrEl1

MPIDR_EL1 — multiprocessor affinity register (per-vCPU; identity).

CntvCtlEl0

CNTV_CTL_EL0 — virtual timer control.

CntvCvalEl0

CNTV_CVAL_EL0 — virtual timer compare value.

CntvOffEl2

CNTV_OFF_EL2 — virtual timer offset.

CntFrqEl0

CNTFRQ_EL0 — counter frequency.

CntKctlEl1

CNTKCTL_EL1 — kernel counter control.

CntpCtlEl0

CNTP_CTL_EL0 — physical timer control.

CntpCvalEl0

CNTP_CVAL_EL0 — physical timer compare value.

PmCcntrEl0

PMCCNTR_EL0 — cycle counter.

PmCcfiltrEl0

PMCCFILTR_EL0 — cycle counter filter.

PmUserEnrEl0

PMUSERENR_EL0 — user enable register.

PmCrEl0

PMCR_EL0 — PMU control.

PmCntEnSetEl0

PMCNTENSET_EL0 — counter enable set.

PmOvsSetEl0

PMOVSSET_EL0 — overflow status set.

PmSelrEl0

PMSELR_EL0 — event counter selection.

EsrEl1

ESR_EL1 — exception syndrome.

FarEl1

FAR_EL1 — fault address register.

Afsr0El1

AFSR0_EL1 — auxiliary fault status register 0.

Afsr1El1

AFSR1_EL1 — auxiliary fault status register 1.

ContextIdrEl1

CONTEXTIDR_EL1 — context ID register.

TpidrEl0

TPIDR_EL0 — thread pointer EL0.

TpidrroEl0

TPIDRRO_EL0 — thread pointer (read-only, EL0).

TpidrEl1

TPIDR_EL1 — thread pointer EL1.

ParEl1

PAR_EL1 — physical address register.

Fpcr

FPCR — FP control register.

Fpsr

FPSR — FP status register.

CpacrEl1

CPACR_EL1 — architectural feature access control.

MdscrEl1

MDSCR_EL1 — monitor debug system control.

OslarEl1

OSLAR_EL1 — OS lock access register.

OsdlrEl1

OSDLR_EL1 — OS double-lock register.

Implementations

impl SysReg

pub fn as_encoded(self) -> u64

A stable wire-encoding for use as a BTreeMap<u64, u64> key in VcpuState::sys_regs.

Each variant carries an explicitly assigned wire constant — reordering Self::all or inserting a new variant in the middle does not change the encoding (the previous positional scheme silently re-keyed every register on a reorder, which would surface as a snapshot mismatch on the next restore, not the build). 0 is reserved for “unknown” and never assigned. Snapshot consumers must round-trip through Self::from_encoded — the wire shape is squib-private (D6).

pub fn from_encoded(key: u64) -> Option<Self>

Inverse of Self::as_encoded. Returns None for keys not in the curated list (forward-compat: a state file from a future squib build that added registers we don’t know about surfaces as None and the loader rejects with SnapshotError::Incompatible).

pub const fn all() -> &'static [SysReg]

All curated sysregs, in canonical order. The order is the additive contract: new registers may be appended; never insert in the middle.

Trait Implementations

impl Clone for SysReg

fn clone(&self) -> SysReg

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SysReg

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for SysReg

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for SysReg

fn eq(&self, other: &SysReg) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for SysReg

impl Eq for SysReg

impl StructuralPartialEq for SysReg