Module layout 

aarch64 memory layout — pinned constants for squib’s microvm.

The fixed layout is sized for the 32-vCPU worst case to defeat the GICR-vs-virtio-MMIO overlap that an earlier draft introduced (D22). The const-evaluated overlap-check at the bottom of this file ensures any future regression breaks the build, not the boot.

See 13-arch-and-boot.md § 2 and 99-key-decisions.md § D22.

Structs

MemoryLayout

Frozen memory layout for a microvm.

PageGeometry

Page geometry constants — three sizes that must never be conflated.

Enums

LayoutOverlap

Result of overlap_check.

Constants

DRAM_BASE

First DRAM byte. Matches Firecracker’s DRAM_MEM_START.

DRAM_MAX_END

Maximum DRAM extent — 0x00FF_8000_0000 matches upstream DRAM_MEM_MAX_SIZE of 1022 GiB above DRAM_BASE.

FDT_MAX_SIZE

FDT region size — at most 2 MiB per arm64/booting.rst.

GICD_BASE

GIC distributor base address.

GICD_RESERVED_SIZE

Maximum GICD region we reserve. The live size is queried from hv_gic_get_distributor_size; this is the placement-only cap.

GICR_BASE

GIC redistributor window base.

GICR_REDISTRIBUTOR_SIZE_PER_VCPU

Worst-case GICR live size (MAX_SUPPORTED_VCPUS × 128 KiB).

GICR_RESERVED_END

End of the GICR reservation window. The live GICR live region must not exceed this.

INITRD_FALLBACK_OFFSET

Initrd start offset: DRAM_BASE + 256 MiB, or kernel_end + 16 MiB rounded up to the 2 MiB grain — whichever is larger. The constant here is the lower bound; the builder computes the actual offset against the kernel size.

KERNEL_LOAD_OFFSET

Kernel image is loaded at DRAM_BASE + KERNEL_LOAD_OFFSET. Matches Firecracker’s reserved 2 MiB for system metadata at the head of DRAM.

MEMORY_LAYOUT

Canonical squib memory layout. There is exactly one — D22 is “fixed”.

MSI_REGION_BASE

MSI region base. HVF’s GIC interception only kicks in once distributor + redistributor + MSI are all configured (skipping MSI causes HVF to silently treat GIC accesses as unmapped, which surfaces as data aborts to the host). We park MSI well below the GICD at a 16 MiB-aligned address. The MSI region itself is sized by hv_gic_get_msi_region_size (typically 64 KiB on macOS 15+); reserve 16 MiB of headroom in case Apple grows it.

PL011_BASE

PL011 UART base. FDT SPI cell 1 → INTID 33, level-high.

PL011_SIZE

PL011 UART region size.

VIRTIO_MMIO_BASE

virtio-MMIO region base.

VIRTIO_MMIO_SIZE

Total virtio-MMIO region size: 32 slots × 4 KiB.

Functions

overlap_check

Runtime layout overlap check used by squib-vmm::builder before hv_gic_create.