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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[derive(Debug)]
pub struct IntelTsxHleSpinLock(UnsafeCell<u8>);
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
impl Default for IntelTsxHleSpinLock
{
#[inline(always)]
fn default() -> Self
{
IntelTsxHleSpinLock(UnsafeCell::new(Self::Unlocked))
}
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
impl SpinLock for IntelTsxHleSpinLock
{
#[inline(always)]
fn acquire_spin_lock(&self)
{
while !self.try_to_acquire_spin_lock()
{
while self.is_locked()
{
spin_loop_hint();
}
}
}
#[inline(always)]
fn try_to_acquire_spin_lock(&self) -> bool
{
let was_previously = unsafe { __hle_acquire_exchange_n1(self.lock(), Self::Locked) };
was_previously == Self::Unlocked
}
#[inline(always)]
fn unlock_spin_lock(&self)
{
debug_assert!(self.is_locked(), "Does not have spin lock");
self.forcibly_unlock_spin_lock()
}
#[inline(always)]
fn is_locked(&self) -> bool
{
unsafe { *self.lock() == Self::Locked }
}
#[inline(always)]
fn is_unlocked(&self) -> bool
{
unsafe { *self.lock() == Self::Unlocked }
}
#[inline(always)]
fn forcibly_unlock_spin_lock(&self)
{
unsafe { __hle_release_store_n1(self.lock(), Self::Unlocked as u32) }
}
}
#[allow(non_upper_case_globals)]
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
impl IntelTsxHleSpinLock
{
const Unlocked: u8 = 0;
const Locked: u8 = 1;
#[inline(always)]
fn lock(&self) -> *mut u8
{
self.0.get()
}
}