[−]Struct solo_bsc::can1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub mcr: MCR,
    pub msr: MSR,
    pub tsr: TSR,
    pub rf0r: RF0R,
    pub rf1r: RF1R,
    pub ier: IER,
    pub esr: ESR,
    pub btr: BTR,
    pub ti0r: TI0R,
    pub tdt0r: TDT0R,
    pub tdl0r: TDL0R,
    pub tdh0r: TDH0R,
    pub ti1r: TI1R,
    pub tdt1r: TDT1R,
    pub tdl1r: TDL1R,
    pub tdh1r: TDH1R,
    pub ti2r: TI2R,
    pub tdt2r: TDT2R,
    pub tdl2r: TDL2R,
    pub tdh2r: TDH2R,
    pub ri0r: RI0R,
    pub rdt0r: RDT0R,
    pub rdl0r: RDL0R,
    pub rdh0r: RDH0R,
    pub ri1r: RI1R,
    pub rdt1r: RDT1R,
    pub rdl1r: RDL1R,
    pub rdh1r: RDH1R,
    pub fmr: FMR,
    pub fm1r: FM1R,
    pub fs1r: FS1R,
    pub ffa1r: FFA1R,
    pub fa1r: FA1R,
    pub f0r1: F0R1,
    pub f0r2: F0R2,
    pub f1r1: F1R1,
    pub f1r2: F1R2,
    pub f2r1: F2R1,
    pub f2r2: F2R2,
    pub f3r1: F3R1,
    pub f3r2: F3R2,
    pub f4r1: F4R1,
    pub f4r2: F4R2,
    pub f5r1: F5R1,
    pub f5r2: F5R2,
    pub f6r1: F6R1,
    pub f6r2: F6R2,
    pub f7r1: F7R1,
    pub f7r2: F7R2,
    pub f8r1: F8R1,
    pub f8r2: F8R2,
    pub f9r1: F9R1,
    pub f9r2: F9R2,
    pub f10r1: F10R1,
    pub f10r2: F10R2,
    pub f11r1: F11R1,
    pub f11r2: F11R2,
    pub f12r1: F12R1,
    pub f12r2: F12R2,
    pub f13r1: F13R1,
    pub f13r2: F13R2,
    pub f14r1: F14R1,
    pub f14r2: F14R2,
    pub f15r1: F15R1,
    pub f15r2: F15R2,
    pub f16r1: F16R1,
    pub f16r2: F16R2,
    pub f17r1: F17R1,
    pub f17r2: F17R2,
    pub f18r1: F18R1,
    pub f18r2: F18R2,
    pub f19r1: F19R1,
    pub f19r2: F19R2,
    pub f20r1: F20R1,
    pub f20r2: F20R2,
    pub f21r1: F21R1,
    pub f21r2: F21R2,
    pub f22r1: F22R1,
    pub f22r2: F22R2,
    pub f23r1: F23R1,
    pub f23r2: F23R2,
    pub f24r1: F24R1,
    pub f24r2: F24R2,
    pub f25r1: F25R1,
    pub f25r2: F25R2,
    pub f26r1: F26R1,
    pub f26r2: F26R2,
    pub f27r1: F27R1,
    pub f27r2: F27R2,
    // some fields omitted
}

Register block

Fields

mcr: MCR

0x00 - master control register

msr: MSR

0x04 - master status register

tsr: TSR

0x08 - transmit status register

rf0r: RF0R

0x0c - receive FIFO 0 register

rf1r: RF1R

0x10 - receive FIFO 1 register

ier: IER

0x14 - interrupt enable register

esr: ESR

0x18 - interrupt enable register

btr: BTR

0x1c - bit timing register

ti0r: TI0R

0x180 - TX mailbox identifier register

tdt0r: TDT0R

0x184 - mailbox data length control and time stamp register

tdl0r: TDL0R

0x188 - mailbox data low register

tdh0r: TDH0R

0x18c - mailbox data high register

ti1r: TI1R

0x190 - mailbox identifier register

tdt1r: TDT1R

0x194 - mailbox data length control and time stamp register

tdl1r: TDL1R

0x198 - mailbox data low register

tdh1r: TDH1R

0x19c - mailbox data high register

ti2r: TI2R

0x1a0 - mailbox identifier register

tdt2r: TDT2R

0x1a4 - mailbox data length control and time stamp register

tdl2r: TDL2R

0x1a8 - mailbox data low register

tdh2r: TDH2R

0x1ac - mailbox data high register

ri0r: RI0R

0x1b0 - receive FIFO mailbox identifier register

rdt0r: RDT0R

0x1b4 - mailbox data high register

rdl0r: RDL0R

0x1b8 - mailbox data high register

rdh0r: RDH0R

0x1bc - receive FIFO mailbox data high register

ri1r: RI1R

0x1c0 - mailbox data high register

rdt1r: RDT1R

0x1c4 - mailbox data high register

rdl1r: RDL1R

0x1c8 - mailbox data high register

rdh1r: RDH1R

0x1cc - mailbox data high register

fmr: FMR

0x200 - filter master register

fm1r: FM1R

0x204 - filter mode register

fs1r: FS1R

0x20c - filter scale register

ffa1r: FFA1R

0x214 - filter FIFO assignment register

fa1r: FA1R

0x21c - filter activation register

f0r1: F0R1

0x240 - Filter bank 0 register 1

f0r2: F0R2

0x244 - Filter bank 0 register 2

f1r1: F1R1

0x248 - Filter bank 1 register 1

f1r2: F1R2

0x24c - Filter bank 1 register 2

f2r1: F2R1

0x250 - Filter bank 2 register 1

f2r2: F2R2

0x254 - Filter bank 2 register 2

f3r1: F3R1

0x258 - Filter bank 3 register 1

f3r2: F3R2

0x25c - Filter bank 3 register 2

f4r1: F4R1

0x260 - Filter bank 4 register 1

f4r2: F4R2

0x264 - Filter bank 4 register 2

f5r1: F5R1

0x268 - Filter bank 5 register 1

f5r2: F5R2

0x26c - Filter bank 5 register 2

f6r1: F6R1

0x270 - Filter bank 6 register 1

f6r2: F6R2

0x274 - Filter bank 6 register 2

f7r1: F7R1

0x278 - Filter bank 7 register 1

f7r2: F7R2

0x27c - Filter bank 7 register 2

f8r1: F8R1

0x280 - Filter bank 8 register 1

f8r2: F8R2

0x284 - Filter bank 8 register 2

f9r1: F9R1

0x288 - Filter bank 9 register 1

f9r2: F9R2

0x28c - Filter bank 9 register 2

f10r1: F10R1

0x290 - Filter bank 10 register 1

f10r2: F10R2

0x294 - Filter bank 10 register 2

f11r1: F11R1

0x298 - Filter bank 11 register 1

f11r2: F11R2

0x29c - Filter bank 11 register 2

f12r1: F12R1

0x2a0 - Filter bank 4 register 1

f12r2: F12R2

0x2a4 - Filter bank 12 register 2

f13r1: F13R1

0x2a8 - Filter bank 13 register 1

f13r2: F13R2

0x2ac - Filter bank 13 register 2

f14r1: F14R1

0x2b0 - Filter bank 14 register 1

f14r2: F14R2

0x2b4 - Filter bank 14 register 2

f15r1: F15R1

0x2b8 - Filter bank 15 register 1

f15r2: F15R2

0x2bc - Filter bank 15 register 2

f16r1: F16R1

0x2c0 - Filter bank 16 register 1

f16r2: F16R2

0x2c4 - Filter bank 16 register 2

f17r1: F17R1

0x2c8 - Filter bank 17 register 1

f17r2: F17R2

0x2cc - Filter bank 17 register 2

f18r1: F18R1

0x2d0 - Filter bank 18 register 1

f18r2: F18R2

0x2d4 - Filter bank 18 register 2

f19r1: F19R1

0x2d8 - Filter bank 19 register 1

f19r2: F19R2

0x2dc - Filter bank 19 register 2

f20r1: F20R1

0x2e0 - Filter bank 20 register 1

f20r2: F20R2

0x2e4 - Filter bank 20 register 2

f21r1: F21R1

0x2e8 - Filter bank 21 register 1

f21r2: F21R2

0x2ec - Filter bank 21 register 2

f22r1: F22R1

0x2f0 - Filter bank 22 register 1

f22r2: F22R2

0x2f4 - Filter bank 22 register 2

f23r1: F23R1

0x2f8 - Filter bank 23 register 1

f23r2: F23R2

0x2fc - Filter bank 23 register 2

f24r1: F24R1

0x300 - Filter bank 24 register 1

f24r2: F24R2

0x304 - Filter bank 24 register 2

f25r1: F25R1

0x308 - Filter bank 25 register 1

f25r2: F25R2

0x30c - Filter bank 25 register 2

f26r1: F26R1

0x310 - Filter bank 26 register 1

f26r2: F26R2

0x314 - Filter bank 26 register 2

f27r1: F27R1

0x318 - Filter bank 27 register 1

f27r2: F27R2

0x31c - Filter bank 27 register 2

Auto Trait Implementations

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

Blanket Implementations

`impl<T> From for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = <U as TryFrom<T>>::Error`

The type returned in the event of a conversion error.

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Borrow for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Same for T`

`type Output = T`

Should always be Self

[−]Struct solo_bsc::can1::RegisterBlock

Fields

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock

Blanket Implementations

impl<T> From for T[src]

fn from(t: T) -> T[src]

impl<T, U> TryFrom for T where U: Into<T>, [src]

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]

impl<T, U> TryInto for T where U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]

impl<T, U> Into for T where U: From<T>, [src]

fn into(self) -> U[src]

impl<T> Borrow for T where T: ?Sized, [src]

fn borrow(&self) -> &T[src]

impl<T> BorrowMut for T where T: ?Sized, [src]

fn borrow_mut(&mut self) -> &mut T[src]

impl<T> Any for T where T: 'static + ?Sized, [src]

fn type_id(&self) -> TypeId[src]

impl<T> Same for T

type Output = T