Module solana_core::sigverify_stage
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The sigverify_stage implements the signature verification stage of the TPU. It
receives a list of lists of packets and outputs the same list, but tags each
top-level list with a list of booleans, telling the next stage whether the
signature in that packet is valid. It assumes each packet contains one
transaction. All processing is done on the CPU by default and on a GPU
if perf-libs are available