Crate sifive_core[][src]

Expand description

Low level access to SiFive RISC-V processor cores

This crate provides:

  • Access to core SiFive CSRs like bpm and feature disable;
  • Access to assemble instructions like CEASE and cache control instructions;
  • High level wrapper for handling SiFive platform features.

Modules

Assembly instructions

Platform specific SiFive CSRs