Module bt_pcm_timing 

Structs

BtPcmTimingSpec

You can read this register and get bt_pcm_timing::R. You can reset, write, write_with_zero this register using bt_pcm_timing::W. You can also modify this register. See API.

Type Aliases

ClkPolR

Field CLK_POL reader - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting

ClkPolW

Field CLK_POL writer - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting

LsbFlagR

Field LSB_FLAG reader - Serial PCM data bit sequence. 0: MSB first, 1: LSB first

LsbFlagW

Field LSB_FLAG writer - Serial PCM data bit sequence. 0: MSB first, 1: LSB first

R

Register BT_PCM_TIMING reader

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

SyncFlagR

Field SYNC_FLAG reader - 0: short sync, 1: long sync

SyncFlagW

Field SYNC_FLAG writer - 0: short sync, 1: long sync

W

Register BT_PCM_TIMING writer