Module audio_serial_timing 

Structs

AudioSerialTimingSpec

You can read this register and get audio_serial_timing::R. You can reset, write, write_with_zero this register using audio_serial_timing::W. You can also modify this register. See API.

Type Aliases

LrckPolR

Field LRCK_POL reader - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih

LrckPolW

Field LRCK_POL writer - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih

R

Register AUDIO_SERIAL_TIMING reader

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

SlaveEnR

Field SLAVE_EN reader - audio code transmit mode select. 0: master mode, 1: slave mode

SlaveEnW

Field SLAVE_EN writer - audio code transmit mode select. 0: master mode, 1: slave mode

TimingR

Field TIMING reader - 00: I2S mode 01: Left justified 10: right justified 11: reserved

TimingW

Field TIMING writer - 00: I2S mode 01: Left justified 10: right justified 11: reserved

W

Register AUDIO_SERIAL_TIMING writer