Expand description
I2C1
Modules§
- bmr
- Bus Monitor Register
- cr
- Control register
- dbr
- Data Buffer register
- dnr
- DMA number register
- fifo
- FIFO Register
- ier
- Interrupt Enable register
- lcr
- Load Count Register
- rccr
- Bus Reset Cycle Counter Register
- rsvd1
- sar
- Slave Address Register
- sr
- Status register
- tcr
- Transfer Control register
- wcr
- Wait Count Register
Structs§
- Register
Block - Register block
Type Aliases§
- Bmr
- BMR (rw) register accessor: Bus Monitor Register
- Cr
- CR (rw) register accessor: Control register
- Dbr
- DBR (rw) register accessor: Data Buffer register
- Dnr
- DNR (rw) register accessor: DMA number register
- Fifo
- FIFO (rw) register accessor: FIFO Register
- Ier
- IER (rw) register accessor: Interrupt Enable register
- Lcr
- LCR (rw) register accessor: Load Count Register
- Rccr
- RCCR (rw) register accessor: Bus Reset Cycle Counter Register
- Rsvd1
- RSVD1 (rw) register accessor:
- Sar
- SAR (rw) register accessor: Slave Address Register
- Sr
- SR (rw) register accessor: Status register
- Tcr
- TCR (rw) register accessor: Transfer Control register
- Wcr
- WCR (rw) register accessor: Wait Count Register