Module cr 

Control register

Structs

CrSpec

Control register

Type Aliases

BrgrstR

Field BRGRST reader - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished

BrgrstW

Field BRGRST writer - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished

DmaenR

Field DMAEN reader - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled

DmaenW

Field DMAEN writer - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled

DnfR

Field DNF reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk … 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode.

DnfW

Field DNF writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk … 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode.

IueR

Field IUE reader - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit.

IueW

Field IUE writer - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit.

LastnackR

Field LASTNACK reader - Generate NACK for last DMA Read transfer

LastnackW

Field LASTNACK writer - Generate NACK for last DMA Read transfer

LaststopR

Field LASTSTOP reader - Generate STOP for last DMA transfer

LaststopW

Field LASTSTOP writer - Generate STOP for last DMA transfer

ModeR

Field MODE reader - Bus Mode (Master operation): 2’b00: standard-mode 2’b01: fast-mode and fast-mode plus 2’b10: HS-mode (standard mode when not doing a high speed transfer) 2’b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2’b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2’b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received.

ModeW

Field MODE writer - Bus Mode (Master operation): 2’b00: standard-mode 2’b01: fast-mode and fast-mode plus 2’b10: HS-mode (standard mode when not doing a high speed transfer) 2’b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2’b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2’b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received.

MsdeR

Field MSDE reader - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled.

MsdeW

Field MSDE writer - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled.

R

Register CR reader

RstreqR

Field RSTREQ reader - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished

RstreqW

Field RSTREQ writer - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished

Rsvd2R

Field RSVD2 reader -

Rsvd2W

Field RSVD2 writer -

Rsvd3R

Field RSVD3 reader -

Rsvd3W

Field RSVD3 writer -

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

ScleR

Field SCLE reader - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation.

ScleW

Field SCLE writer - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation.

SclppR

Field SCLPP reader - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL

SclppW

Field SCLPP writer - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL

SlvenR

Field SLVEN reader - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus.

SlvenW

Field SLVEN writer - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus.

UrR

Field UR reader - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module.

UrW

Field UR writer - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module.

W

Register CR writer