Type Alias W 

pub type W = W<FifoCtrlSpec>;

Register FIFO_CTRL writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn tft(&mut self) -> TftW<'_, FifoCtrlSpec>

Bits 0:4 - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

pub fn rft(&mut self) -> RftW<'_, FifoCtrlSpec>

Bits 5:9 - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

pub fn tsre(&mut self) -> TsreW<'_, FifoCtrlSpec>

Bit 10 - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

pub fn rsre(&mut self) -> RsreW<'_, FifoCtrlSpec>

Bit 11 - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

pub fn rxfifo_rd_endian(&mut self) -> RxfifoRdEndianW<'_, FifoCtrlSpec>

Bits 12:13 - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0] 0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]} 0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]} 0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]}

pub fn txfifo_wr_endian(&mut self) -> TxfifoWrEndianW<'_, FifoCtrlSpec>

Bits 14:15 - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata[31:0] = apb_pwdata[31:0] 0x1 = fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]} 0x2 = txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]} 0x3 = txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]}

pub fn fpcke(&mut self) -> FpckeW<'_, FifoCtrlSpec>

Bit 16 - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled

pub fn rxfifo_auto_full_ctrl(&mut self) -> RxfifoAutoFullCtrlW<'_, FifoCtrlSpec>

Bit 17 - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control

pub fn efwr(&mut self) -> EfwrW<'_, FifoCtrlSpec>

Bit 18 - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled

pub fn strf(&mut self) -> StrfW<'_, FifoCtrlSpec>

Bit 19 - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register

pub fn rsvd(&mut self) -> RsvdW<'_, FifoCtrlSpec>

Bits 20:31