[][src]Module sam3x8e::dmac

DMA Controller

Modules

cfg0

DMAC Channel Configuration Register (ch_num = 0)

cfg1

DMAC Channel Configuration Register (ch_num = 1)

cfg2

DMAC Channel Configuration Register (ch_num = 2)

cfg3

DMAC Channel Configuration Register (ch_num = 3)

cfg4

DMAC Channel Configuration Register (ch_num = 4)

cfg5

DMAC Channel Configuration Register (ch_num = 5)

chdr

DMAC Channel Handler Disable Register

cher

DMAC Channel Handler Enable Register

chsr

DMAC Channel Handler Status Register

creq

DMAC Software Chunk Transfer Request Register

ctrla0

DMAC Channel Control A Register (ch_num = 0)

ctrla1

DMAC Channel Control A Register (ch_num = 1)

ctrla2

DMAC Channel Control A Register (ch_num = 2)

ctrla3

DMAC Channel Control A Register (ch_num = 3)

ctrla4

DMAC Channel Control A Register (ch_num = 4)

ctrla5

DMAC Channel Control A Register (ch_num = 5)

ctrlb0

DMAC Channel Control B Register (ch_num = 0)

ctrlb1

DMAC Channel Control B Register (ch_num = 1)

ctrlb2

DMAC Channel Control B Register (ch_num = 2)

ctrlb3

DMAC Channel Control B Register (ch_num = 3)

ctrlb4

DMAC Channel Control B Register (ch_num = 4)

ctrlb5

DMAC Channel Control B Register (ch_num = 5)

daddr0

DMAC Channel Destination Address Register (ch_num = 0)

daddr1

DMAC Channel Destination Address Register (ch_num = 1)

daddr2

DMAC Channel Destination Address Register (ch_num = 2)

daddr3

DMAC Channel Destination Address Register (ch_num = 3)

daddr4

DMAC Channel Destination Address Register (ch_num = 4)

daddr5

DMAC Channel Destination Address Register (ch_num = 5)

dscr0

DMAC Channel Descriptor Address Register (ch_num = 0)

dscr1

DMAC Channel Descriptor Address Register (ch_num = 1)

dscr2

DMAC Channel Descriptor Address Register (ch_num = 2)

dscr3

DMAC Channel Descriptor Address Register (ch_num = 3)

dscr4

DMAC Channel Descriptor Address Register (ch_num = 4)

dscr5

DMAC Channel Descriptor Address Register (ch_num = 5)

ebcidr

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.

ebcier

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.

ebcimr

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.

ebcisr

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.

en

DMAC Enable Register

gcfg

DMAC Global Configuration Register

last

DMAC Software Last Transfer Flag Register

saddr0

DMAC Channel Source Address Register (ch_num = 0)

saddr1

DMAC Channel Source Address Register (ch_num = 1)

saddr2

DMAC Channel Source Address Register (ch_num = 2)

saddr3

DMAC Channel Source Address Register (ch_num = 3)

saddr4

DMAC Channel Source Address Register (ch_num = 4)

saddr5

DMAC Channel Source Address Register (ch_num = 5)

sreq

DMAC Software Single Request Register

wpmr

DMAC Write Protect Mode Register

wpsr

DMAC Write Protect Status Register

Structs

CFG0

DMAC Channel Configuration Register (ch_num = 0)

CFG1

DMAC Channel Configuration Register (ch_num = 1)

CFG2

DMAC Channel Configuration Register (ch_num = 2)

CFG3

DMAC Channel Configuration Register (ch_num = 3)

CFG4

DMAC Channel Configuration Register (ch_num = 4)

CFG5

DMAC Channel Configuration Register (ch_num = 5)

CHDR

DMAC Channel Handler Disable Register

CHER

DMAC Channel Handler Enable Register

CHSR

DMAC Channel Handler Status Register

CREQ

DMAC Software Chunk Transfer Request Register

CTRLA0

DMAC Channel Control A Register (ch_num = 0)

CTRLA1

DMAC Channel Control A Register (ch_num = 1)

CTRLA2

DMAC Channel Control A Register (ch_num = 2)

CTRLA3

DMAC Channel Control A Register (ch_num = 3)

CTRLA4

DMAC Channel Control A Register (ch_num = 4)

CTRLA5

DMAC Channel Control A Register (ch_num = 5)

CTRLB0

DMAC Channel Control B Register (ch_num = 0)

CTRLB1

DMAC Channel Control B Register (ch_num = 1)

CTRLB2

DMAC Channel Control B Register (ch_num = 2)

CTRLB3

DMAC Channel Control B Register (ch_num = 3)

CTRLB4

DMAC Channel Control B Register (ch_num = 4)

CTRLB5

DMAC Channel Control B Register (ch_num = 5)

DADDR0

DMAC Channel Destination Address Register (ch_num = 0)

DADDR1

DMAC Channel Destination Address Register (ch_num = 1)

DADDR2

DMAC Channel Destination Address Register (ch_num = 2)

DADDR3

DMAC Channel Destination Address Register (ch_num = 3)

DADDR4

DMAC Channel Destination Address Register (ch_num = 4)

DADDR5

DMAC Channel Destination Address Register (ch_num = 5)

DSCR0

DMAC Channel Descriptor Address Register (ch_num = 0)

DSCR1

DMAC Channel Descriptor Address Register (ch_num = 1)

DSCR2

DMAC Channel Descriptor Address Register (ch_num = 2)

DSCR3

DMAC Channel Descriptor Address Register (ch_num = 3)

DSCR4

DMAC Channel Descriptor Address Register (ch_num = 4)

DSCR5

DMAC Channel Descriptor Address Register (ch_num = 5)

EBCIDR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.

EBCIER

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.

EBCIMR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.

EBCISR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.

EN

DMAC Enable Register

GCFG

DMAC Global Configuration Register

LAST

DMAC Software Last Transfer Flag Register

RegisterBlock

Register block

SADDR0

DMAC Channel Source Address Register (ch_num = 0)

SADDR1

DMAC Channel Source Address Register (ch_num = 1)

SADDR2

DMAC Channel Source Address Register (ch_num = 2)

SADDR3

DMAC Channel Source Address Register (ch_num = 3)

SADDR4

DMAC Channel Source Address Register (ch_num = 4)

SADDR5

DMAC Channel Source Address Register (ch_num = 5)

SREQ

DMAC Software Single Request Register

WPMR

DMAC Write Protect Mode Register

WPSR

DMAC Write Protect Status Register