Crate s32k116_pac
source · [−]Expand description
Peripheral access API for S32K116 microcontrollers (generated using svd2rust v0.21.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Modules
Analog-to-Digital Converter
AIPS-Lite Bridge
Flex Controller Area Network module
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMU_FC
CMU_FC
Cyclic Redundancy Check
CSE_PRAM
Enhanced Direct Memory Access
DMA channel multiplexor
Error Injection Module
ERM
The FLEXIO Memory Map/Register Definition can be found here.
FTFC
FlexTimer Module
FlexTimer Module
Common register and bit access and modify traits
Local Memory Controller
The LPI2C Memory Map/Register Definition can be found here.
Low Power Periodic Interrupt Timer (LPIT)
The LPSPI Memory Map/Register Definition can be found here.
Low Power Timer
Universal Asynchronous Receiver/Transmitter
Universal Asynchronous Receiver/Transmitter
Core Platform Miscellaneous Control Module
MSCM
MTB data watchpoint and trace
PCC
Programmable Delay Block
PMC
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
Reset Control Module
Secure Real Time Clock
Nested Vectored Interrupt Controller
System Control Registers
System timer
System Clock Generator
System Integration Module
System Mode Controller
TRGMUX
Watchdog timer
Structs
Analog-to-Digital Converter
AIPS-Lite Bridge
Flex Controller Area Network module
Cache and branch predictor maintenance operations
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMU_FC
CMU_FC
CPUID
Cyclic Redundancy Check
CSE_PRAM
Core peripherals
Debug Control Block
Enhanced Direct Memory Access
DMA channel multiplexor
Data Watchpoint and Trace unit
Error Injection Module
ERM
The FLEXIO Memory Map/Register Definition can be found here.
Flash Patch and Breakpoint unit
Floating Point Unit
FTFC
FlexTimer Module
FlexTimer Module
Instrumentation Trace Macrocell
Local Memory Controller
The LPI2C Memory Map/Register Definition can be found here.
Low Power Periodic Interrupt Timer (LPIT)
The LPSPI Memory Map/Register Definition can be found here.
Low Power Timer
Universal Asynchronous Receiver/Transmitter
Universal Asynchronous Receiver/Transmitter
Core Platform Miscellaneous Control Module
Memory Protection Unit
MSCM
MTB data watchpoint and trace
Nested Vector Interrupt Controller
PCC
Programmable Delay Block
PMC
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
Pin Control and Interrupts
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
All the peripherals
Reset Control Module
Secure Real Time Clock
Nested Vectored Interrupt Controller
System Control Registers
System timer
System Control Block
System Clock Generator
System Integration Module
System Mode Controller
SysTick: System Timer
Trace Port Interface Unit
TRGMUX
Watchdog timer
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority