Module s2pac_ch32v103::usart1
source · Expand description
Universal synchronous asynchronous receiver transmitter
Modules§
- Baud rate register
- Control register 1
- Control register 2
- Control register 3
- Data register
- Guard time and prescaler register
- Status register
Structs§
- Register block
Type Aliases§
- BRR (rw) register accessor: Baud rate register
- CTLR1 (rw) register accessor: Control register 1
- CTLR2 (rw) register accessor: Control register 2
- CTLR3 (rw) register accessor: Control register 3
- DATAR (rw) register accessor: Data register
- GPR (rw) register accessor: Guard time and prescaler register
- STATR (rw) register accessor: Status register