Module s2pac_ch32v103::tim1

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Advanced timer

Modules§

Structs§

Type Aliases§

  • ATRLR
    ATRLR (rw) register accessor: auto-reload register
  • BDTR
    BDTR (rw) register accessor: break and dead-time register
  • CCER
    CCER (rw) register accessor: capture/compare enable register
  • CH1CVR
    CH1CVR (rw) register accessor: capture/compare register 1
  • CH2CVR
    CH2CVR (rw) register accessor: capture/compare register 2
  • CH3CVR
    CH3CVR (rw) register accessor: capture/compare register 3
  • CH4CVR
    CH4CVR (rw) register accessor: capture/compare register 4
  • CHCTLR1_INPUT
    CHCTLR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
  • CHCTLR1_OUTPUT
    CHCTLR1_Output (rw) register accessor: capture/compare mode register (output mode)
  • CHCTLR2_INPUT
    CHCTLR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
  • CHCTLR2_OUTPUT
    CHCTLR2_Output (rw) register accessor: capture/compare mode register (output mode)
  • CNT
    CNT (rw) register accessor: counter
  • CTLR1
    CTLR1 (rw) register accessor: control register 1
  • CTLR2
    CTLR2 (rw) register accessor: control register 2
  • DMACFGR
    DMACFGR (rw) register accessor: DMA control register
  • DMAINTENR
    DMAINTENR (rw) register accessor: DMA/Interrupt enable register
  • DMAR
    DMAR (rw) register accessor: DMA address for full transfer
  • INTFR
    INTFR (rw) register accessor: status register
  • PSC
    PSC (rw) register accessor: prescaler
  • RPTCR
    RPTCR (rw) register accessor: repetition counter register
  • SMCFGR
    SMCFGR (rw) register accessor: slave mode control register
  • SWEVGR
    SWEVGR (w) register accessor: event generation register