Module s2pac_ch32v103::dac1

Digital to analog converter

Modules

• ctlr
  Control register (DAC_CTLR)
• dor1
  DAC channel1 data output register (DAC_DOR1)
• dor2
  DAC channel2 data output register (DAC_DOR2)
• l12bdhr1
  DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)
• l12bdhr2
  DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)
• r12bdhr1
  DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)
• r12bdhr2
  DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)
• swtr
  DAC software trigger register (DAC_SWTR)

Structs

• RegisterBlock
  Register block

Type Aliases

• CTLR
  CTLR (rw) register accessor: Control register (DAC_CTLR)
• DOR1
  DOR1 (r) register accessor: DAC channel1 data output register (DAC_DOR1)
• DOR2
  DOR2 (r) register accessor: DAC channel2 data output register (DAC_DOR2)
• L12BDHR1
  L12BDHR1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)
• L12BDHR2
  L12BDHR2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)
• R12BDHR1
  R12BDHR1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)
• R12BDHR2
  R12BDHR2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)
• SWTR
  SWTR (w) register accessor: DAC software trigger register (DAC_SWTR)