Module s2pac_ch32v103::dac1
source · Expand description
Digital to analog converter
Modules§
- Control register (DAC_CTLR)
- DAC channel1 data output register (DAC_DOR1)
- DAC channel2 data output register (DAC_DOR2)
- DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)
- DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)
- DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)
- DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)
- DAC software trigger register (DAC_SWTR)
Structs§
- Register block
Type Aliases§
- CTLR (rw) register accessor: Control register (DAC_CTLR)
- DOR1 (r) register accessor: DAC channel1 data output register (DAC_DOR1)
- DOR2 (r) register accessor: DAC channel2 data output register (DAC_DOR2)
- L12BDHR1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1)
- L12BDHR2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2)
- R12BDHR1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1)
- R12BDHR2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2)
- SWTR (w) register accessor: DAC software trigger register (DAC_SWTR)