[][src]Module rysk_core::system

Structs

Core

A single RISCV core. Includes a single program counter and 32 registers. Const generics will allow support of the E extensions for 16 registers.

Enums

Exception

An exception thrown by a hart during instruction decoding and execution

Traits

Mmu

A Memory Management Unit (MMU) handles memory accesses on the system. Devices and memory regions other than working memory (ie. RAM) may be mapped by way of the MMU.