[−][src]Module rvemu::csr
The csr module contains all the control and status registers.
Modules
| fcsr | |
| marchid | |
| mcause | |
| medeleg | |
| mepc | |
| mhartid | |
| mideleg | |
| mie | |
| mimpid | |
| mip | |
| misa | |
| mscratch | |
| mstatus | |
| mtvec | Machine trap-handler base address. |
| mvendorid | |
| pmpaddr0 | |
| pmpcfg0 | |
| satp | Supervisor address translation and protection. |
| scause | |
| sepc | |
| sstatus | |
| stvec | |
| uepc |
Structs
| State | The state to contains all the CSRs. |
Enums
| Csr | All kinds of CSRs. |
Constants
| FCSR | Floating-point control and status register (frm + fflags). |
| FFLAGS | Flating-point accrued exceptions. |
| FRB | Floating-point dynamic rounding mode. |
| MARCHID | Architecture ID. |
| MCAUSE | Machine trap cause. |
| MCOUNTEREN | Machine counter enable. |
| MEDELEG | Machine exception delefation register. |
| MEPC | Machine exception program counter. |
| MHARTID | Hardware thread ID. |
| MIDELEG | Machine interrupt delefation register. |
| MIE | Machine interrupt-enable register. |
| MIMPID | Implementation ID. |
| MIP | Machine interrupt pending. |
| MISA | ISA and extensions. |
| MSCRATCH | Scratch register for machine trap handlers. |
| MSTATUS | Machine status register. |
| MTVAL | Machine bad address or instruction. |
| MTVEC | Machine trap-handler base address. |
| MVENDORID | Vendor ID. |
| MXLEN | |
| PMPADDR0 | Physical memory protection address register. |
| PMPCFG0 | Physical memory protection configuration. |
| SATP | Supervisor address translation and protection. |
| SCAUSE | Supervisor trap cause. |
| SEPC | Supervisor exception program counter. |
| SSTATUS | Supervisor status register. |
| STVEC | Supervisor trap handler base address. |
| UCAUSE | User trap cause. |
| UEPC | User exception program counter. |
Traits
| CsrBase | |
| Read | The trait of reading the value which all CSRs should implement. |
| Write | The trait of writing the value which all CSRs should implement. |
Type Definitions
| CsrAddress | |
| Mxlen |