[−][src]Module rv32m1_ri5cy_pac::usdhc0
uSDHC
Modules
| adma_err_status | ADMA Error Status Register |
| adma_sys_addr | ADMA System Address |
| autocmd12_err_status | Auto CMD12 Error Status |
| blk_att | Block Attributes |
| cmd_arg | Command Argument |
| cmd_rsp0 | Command Response0 |
| cmd_rsp1 | Command Response1 |
| cmd_rsp2 | Command Response2 |
| cmd_rsp3 | Command Response3 |
| cmd_xfr_typ | Command Transfer Type |
| data_buff_acc_port | Data Buffer Access Port |
| ds_addr | DMA System Address |
| force_event | Force Event |
| host_ctrl_cap | Host Controller Capabilities |
| int_signal_en | Interrupt Signal Enable |
| int_status | Interrupt Status |
| int_status_en | Interrupt Status Enable |
| mix_ctrl | Mixer Control |
| mmc_boot | MMC Boot Register |
| pres_state | Present State |
| prot_ctrl | Protocol Control |
| sys_ctrl | System Control |
| vend_spec | Vendor Specific Register |
| vend_spec2 | Vendor Specific 2 Register |
| wtmk_lvl | Watermark Level |
Structs
| RegisterBlock | Register block |
Type Definitions
| ADMA_ERR_STATUS | ADMA Error Status Register |
| ADMA_SYS_ADDR | ADMA System Address |
| AUTOCMD12_ERR_STATUS | Auto CMD12 Error Status |
| BLK_ATT | Block Attributes |
| CMD_ARG | Command Argument |
| CMD_RSP0 | Command Response0 |
| CMD_RSP1 | Command Response1 |
| CMD_RSP2 | Command Response2 |
| CMD_RSP3 | Command Response3 |
| CMD_XFR_TYP | Command Transfer Type |
| DATA_BUFF_ACC_PORT | Data Buffer Access Port |
| DS_ADDR | DMA System Address |
| FORCE_EVENT | Force Event |
| HOST_CTRL_CAP | Host Controller Capabilities |
| INT_SIGNAL_EN | Interrupt Signal Enable |
| INT_STATUS | Interrupt Status |
| INT_STATUS_EN | Interrupt Status Enable |
| MIX_CTRL | Mixer Control |
| MMC_BOOT | MMC Boot Register |
| PRES_STATE | Present State |
| PROT_CTRL | Protocol Control |
| SYS_CTRL | System Control |
| VEND_SPEC | Vendor Specific Register |
| VEND_SPEC2 | Vendor Specific 2 Register |
| WTMK_LVL | Watermark Level |