[−][src]Module rv32m1_ri5cy_pac::scg::vccr

VLPR Clock Control Register

Structs

DIVBUS_W	Write proxy for field `DIVBUS`
DIVCORE_W	Write proxy for field `DIVCORE`
DIVEXT_W	Write proxy for field `DIVEXT`
DIVSLOW_W	Write proxy for field `DIVSLOW`
SCS_W	Write proxy for field `SCS`

Enums

DIVBUS_A	Bus Clock Divide Ratio
DIVCORE_A	Core Clock Divide Ratio
DIVEXT_A	External Clock Divide Ratio
DIVSLOW_A	Slow Clock Divide Ratio
SCS_A	System Clock Source

Type Definitions

DIVBUS_R	Reader of field `DIVBUS`
DIVCORE_R	Reader of field `DIVCORE`
DIVEXT_R	Reader of field `DIVEXT`
DIVSLOW_R	Reader of field `DIVSLOW`
R	Reader of register VCCR
SCS_R	Reader of field `SCS`
W	Writer for register VCCR