Struct rust_hdl::bsp::ok_xem7010::ddr_fifo7::DDR7FIFO

pub struct DDR7FIFO<const N: usize> {

    pub reset: Signal<In, Bit>,
    pub sys_clock_p: Signal<In, Clock>,
    pub sys_clock_n: Signal<In, Clock>,
    pub mcb: MCBInterface4GDDR3,
    pub data_in: Signal<In, Bits<N>>,
    pub full: Signal<Out, Bit>,
    pub write: Signal<In, Bit>,
    pub write_clock: Signal<In, Clock>,
    pub data_out: Signal<Out, Bits<N>>,
    pub empty: Signal<Out, Bit>,
    pub read: Signal<In, Bit>,
    pub read_clock: Signal<In, Clock>,
    pub status: Signal<Out, Bits<8>>,
    /* private fields */
}

Fields

reset: Signal<In, Bit>

sys_clock_p: Signal<In, Clock>

sys_clock_n: Signal<In, Clock>

mcb: MCBInterface4GDDR3

data_in: Signal<In, Bits<N>>

full: Signal<Out, Bit>

write: Signal<In, Bit>

write_clock: Signal<In, Clock>

data_out: Signal<Out, Bits<N>>

empty: Signal<Out, Bit>

read: Signal<In, Bit>

read_clock: Signal<In, Clock>

status: Signal<Out, Bits<8>>

Trait Implementations

impl<const N: usize> Block for DDR7FIFO<N>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const N: usize> Default for DDR7FIFO<N>

fn default() -> DDR7FIFO<N>

Returns the “default value” for a type.

impl<const N: usize> Logic for DDR7FIFO<N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog