1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

use rust_hdl_core::prelude::*;

#[derive(LogicBlock, Default)]
pub struct OpenDrainBuffer {
    pub bus: Signal<InOut, Bit>,
    pub control: OpenDrainReceiver,
}

impl Logic for OpenDrainBuffer {
    fn update(&mut self) {
        if self.control.drive_low.val() {
            self.bus.next = false;
        }
        self.control.line_state.next = self.bus.val();
        self.bus
            .set_tristate_is_output(self.control.drive_low.val());
    }

    fn connect(&mut self) {
        self.bus.connect();
        self.control.line_state.connect();
    }

    fn hdl(&self) -> Verilog {
        Verilog::Custom(format!(
            "\
    assign bus = control$drive_low ? 0 : 1'bz;
    always @(*) control$line_state = bus;"
        ))
    }
}

#[test]
fn test_opendrain_synthesizes() {
    let mut uut = OpenDrainBuffer::default();
    uut.connect_all();
    let vlog = generate_verilog(&uut);
    println!("{}", vlog);
    yosys_validate("open_drain", &vlog).unwrap()
}

#[derive(LogicInterface, Default)]
#[join = "OpenDrainReceiver"]
pub struct OpenDrainDriver {
    pub drive_low: Signal<Out, Bit>,
    pub line_state: Signal<In, Bit>,
}

#[derive(LogicInterface, Default)]
#[join = "OpenDrainDriver"]
pub struct OpenDrainReceiver {
    pub drive_low: Signal<In, Bit>,
    pub line_state: Signal<Out, Bit>,
}