Struct rust_hdl_hls::mosi_port::MOSIPort

pub struct MOSIPort<const D: usize> {
    pub bus: SoCPortResponder<D>,
    pub port_out: Signal<Out, Bits<D>>,
    pub strobe_out: Signal<Out, Bit>,
    pub ready: Signal<In, Bit>,
    pub clock_out: Signal<Out, Clock>,
    /* private fields */
}

Fields

bus: SoCPortResponder<D>

port_out: Signal<Out, Bits<D>>

strobe_out: Signal<Out, Bit>

ready: Signal<In, Bit>

clock_out: Signal<Out, Clock>

Trait Implementations

impl<const D: usize> Block for MOSIPort<D>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const D: usize> Default for MOSIPort<D>

fn default() -> MOSIPort<D>

Returns the “default value” for a type.

impl<const D: usize> Logic for MOSIPort<D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>