Module ruspiro_register::system::aarch64::tcr_el1

This is supported on AArch64 only.

TCR_EL1 - Translation Control Register EL1

Determines which Translation Base Registers defines the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1 and holds cacheability and shareability information.

Usage Constraints

EL0	EL1 (NS)	EL1(S)	EL2	EL3(NS)	EL3(S)
-	R/W	R/W	R/W	R/W	R/W

Modules

A1	AArch64 ASID definition by TTBR0_EL1 or TTBR1_EL1
AS	AArch64 ASID size
EPD0	AArch64 Disable tlb walks using ttbr0_el1
EPD1	AArch64 disable tlb walks using ttbr1_el1
IPS	AArch64 Intermediate Physical address size
IRGN0	AArch64 Inner cacheability attribute for memory associated with tlb walks using ttbr0_el1
IRGN1	AArch64 Inner cacheability attribute for memory associated with tlb walks using ttbr1_el1
ORGN0	AArch64 Outer cacheability attribute for memory associated with tlb walks using ttbr0_el1
ORGN1	AArch64 Outer cacheability attribute for memory associated with tlb walks using ttbr1_el1
SH0	AArch64 Shareability attribute for memory associated with tlb walks using ttbr0_el1
SH1	AArch64 Shareability attribute for memory associated with tlb walks using ttbr1_el1
T0SZ	AArch64 Size offset of the memory reagion addressed by ttbr0_el1 (size = 2^(64-t0sz))
T1SZ	AArch64 Size offset of the memory reagion addressed by ttbr1_el1 (size = 2^(64-t0sz))
TBI0	AArch64 Top Byte Ignored for ttbr0_el1
TBI1	AArch64 Top Byte Ignored for ttbr1_el1
TG0	AArch64 Granule size for the ttbr0_el2
TG1	AArch64 Granule size for the ttbr0_el2

Functions

get	AArch64 Read the raw register contents using the appropriate assembly
read	AArch64 Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required
set	AArch64 Write the raw register contents using the appropriate contents
write	AArch64 Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.