[−][src]Module ruspiro_register::system::aarch64::hcr_el2

This is supported on AArch64 only.

HCR_EL2 - Hypervisor Configuration Register

Provides configuration control for virtualization, including whether various Non-secure operations are trapped to EL2.

Usage Constraints

EL0EL1 (NS)EL1(S)EL2EL3(NS)EL3(S)
---R/WR/WR/W

Modules

AMOAArch64

Async Abort and Error exception routing to EL2

BSUAArch64

Barrier sharability upgrade

CDAArch64

disable stage 2 data cache

DCAArch64

default cacheable

FBAArch64

Forces broadcast

FMOAArch64

physical FIQ routing to EL2

IDAArch64

disable stage 2 instruction cache

IMOAArch64

phyiscal IRQ routing to EL2

PTWAArch64
RWAArch64

register width control for lower exception levels

TACRAArch64

trap auxiliry control registers

TDZAArch64

trap dc zva instruction

TGEAArch64

trap generel exceptions

TID0AArch64

trap ID group 0 registers

TID1AArch64

trap ID group 1 registers

TID2AArch64

trap ID group 2 registers

TID3AArch64

trap ID group 3 registers

TIDCPAArch64

trap implementation depended instructions

TPCAArch64

trap data or unified cache maintenance instructions to Point of Coherency

TPUAArch64

trap data or nuified cache maintenance instructions to Point of Unification

TRVMAArch64

trap reads of virtual memory controls

TSCAArch64

trap SMC instruction

TSWAArch64

trap data or unified cache maintenenace instructions by set or way

TTLBAArch64

trap ttlb maintenance instructions

TVMAArch64

trap virtual memory control

TWEAArch64

trap WFE if there is no pending WFE event

TWIAArch64

trap WFI if there is no pending WFI event

VFAArch64

virtual FIQ pending

VIAArch64

virtual IRQ pending

VMAArch64

enable second stage of translation

VSEAArch64

virtual system error/async abort pending

Functions

getAArch64

Read the raw register contents using the appropriate assembly

readAArch64

Read the contents of a specific RegisterField. The returned value is already shifted to the right to start at bit 0. This means for a field value stored in the register at bit offset 3, the returned value is already shifted by 3 bits to the right. For example: If register raw value is 0b10110, the returned value for a register field specified as bits[4:3] would be 0b01. No further "masking" or "bit-shift" required

setAArch64

Write the raw register contents using the appropriate contents

writeAArch64

Update the contents of a register from the RegisterFieldValue given. This will only change the bits the RegisterField definition specifies.